Fringe capacitor using bootstrapped non-metal layer
Capacitors configured in a switched-capacitor circuit on a semiconductor device may comprise very accurately matched, high capacitance density metal-to-metal capacitors, using top-plate-to-bottom-plate fringe-capacitance for obtaining the desired capacitance values. A polysilicon plate may be inserted below the bottom metal layer as a shield, and bootstrapped to the top plate of each capacitor in order to minimize and/or eliminate the parasitic top-plate-to-substrate capacitance. This may free up the bottom metal layer to be used in forming additional fringe-capacitance, thereby increasing capacitance density. By forming each capacitance solely based on fringe-capacitance from the top plate to the bottom plate, no parallel-plate-capacitance is used, which may reduce capacitor mismatch. Parasitic bottom plate capacitance to the substrate may also be eliminated, with only a small capacitance to the bootstrapped polysilicon plate remaining. The capacitors may be bootstrapped by coupling the top plate of each capacitor to a respective one of the differential inputs of an amplifier comprised in the switched-capacitor circuit.
1. A capacitor on a semiconductor having accurate, high density capacitance between a first node corresponding to a top plate of the capacitor and a second node corresponding to a bottom plate of the capacitor, the capacitor comprising:
one or more layers of conductive strips forming the capacitor, wherein for each pair of neighboring conductive strips within each of the one or more layers of conductive strips:
a first conductive strip of the pair of neighboring conductive strips is coupled to the first node and not to the second node; and
a second conductive strip of the pair of neighboring conductive strips is coupled to the second node and not to the first node; and
a low-impedance conductive layer configured beneath a bottom layer of the one or more layers of conductive strips, and spanning an area underneath conductive strips coupled to the first node and conductive strips coupled to the second node, wherein the low-impedance conductive layer is electrically coupled to the first node and not to the second node to reduce charge transfers from the first node to the low-impedance conductive layer.
2. The capacitor of claim 1 , wherein the low-impedance conductive layer is coupled to the first node to reduce parasitic capacitance from the second node to a substrate of the semiconductor in addition to reducing charge transfers from the first node to the low-impedance conductive plate.
3. The capacitor of claim 1 , wherein the one or more layers of conductive strips are aligned so that conductive strips coupled to the first node lie above other conductive strips coupled to the first node.
4. The capacitor of claim 3 , wherein the one or more layers of conductive strips are aligned so that conductive strips coupled to the second node lie above other conductive strips coupled to the second node.
5. The capacitor structure of claim 1 , wherein the low-impedance conductive layer is a low-impedance conductive plate.
6. The capacitor of claim 5 , wherein the low-impedance conductive layer comprises one of:
a solid planar low-impedance conductive material; and
a plurality of low-impedance conductive strips.
7. A semiconductor device comprising a capacitor, the semiconductor device comprising:
one or more layers of conductive strips forming the capacitor, wherein for each pair of neighboring conductive strips within each of the one or more layers of conductive strips:
a first conductive strip of the pair of neighboring conductive strips is coupled to the first node and not to the second node; and
a second conductive strip of the pair of neighboring conductive strips is coupled to the second node and not to the first node; and
a low-impedance conductive layer configured beneath a bottom layer of the one or more layers of conductive strips, and spanning an area underneath conductive strips coupled to the first node and conductive strips coupled to the second node, wherein the low-impedance conductive layer is electrically coupled to the first node and not to the second node to reduce charge transfers from the first node to the low-impedance conductive layer;
wherein the capacitor has an accurate, high density capacitance between a first node corresponding to a top plate of the capacitor and a second node corresponding to a bottom plate of the capacitor.