Method and apparatus providing reduced metal routing in imagers

1. An imaging device, comprising:

a pixel array having a plurality of pixels arranged in rows and columns, at least one pixel of the array comprising:

a photosensor;

a first reset transistor operable to reset the photosensor, wherein the first reset transistor has a first source-drain terminal, a second source-drain terminal, and a gate terminal and wherein the first source-drain terminal of the first reset transistor is coupled to the photosensor;

a global reset line, wherein the gate terminal and the second source-drain terminal of the first reset transistor are coupled to the global reset line;

a first storage node including a floating diffusion region operable to store charges generated by the photosensor;

a second storage node operable to store the charges generated by the photosensor;

a first transfer transistor operable to transfer the charges generated by the photosensor from the photosensor to the second storage node;

a second transfer transistor operable to transfer the charges generated by the photosensor from the second storage node to the floating diffusion region of the first storage node; and

a second reset transistor operable to reset the floating diffusion region of the first storage node, wherein the second reset transistor has a first source-drain terminal, a second source-drain terminal, and a gate terminal, wherein the first source-drain terminal of the second reset transistor is coupled to the floating diffusion region of the first storage node, wherein the gate terminal and the second source-drain terminal of the second reset transistor are coupled to a column line.

2. The imaging device of claim 1 , wherein the column line that the gate terminal and the second source-drain terminal of the second reset transistor are coupled to comprises a column output line.

3. The imaging device of claim 2 further comprising:

a latch up circuit for switchably placing an array voltage on the column output line.

4. The imaging device of claim 3 further comprising:

a capacitor having a first terminal coupled to the floating diffusion region and having a second terminal operable to receive the array voltage;

a source-follower transistor having a gate terminal coupled to the floating diffusion region of the first storage node, having a first source-drain terminal operable to receive the array voltage, and having a second source-drain terminal; and

a row-select transistor having a gate terminal operable to receive row select signals from a row select line, having a first source-drain terminal coupled to the second source-drain terminal of the source-follow transistor, and having a second source-drain terminal coupled to the column line to which the gate terminal and the second source-drain terminal of the second reset transistor are coupled.

5. An imaging pixel comprising:

a photosensor;

a first reset transistor, wherein the first reset transistor has a first source-drain terminal, a second source-drain terminal, and a gate terminal;

an output line, wherein at least one of the terminals of the first reset transistor is coupled to the output line, wherein the gate terminal and the first source-drain terminal of the first reset transistor are coupled to the output line;

a reset line; and

a second reset transistor having first and second source-drain terminals and a gate terminal, wherein the first source-drain terminal and the gate terminal of the second reset transistor are coupled to the reset line.

6. The imaging pixel defined in claim 5 further comprising:

a first storage node including a floating diffusion region for storing charges generated by the photosensor; and

a second storage node for storing the charged generated by the photosensor.

7. The imaging pixel defined in claim 6 wherein the second source-drain terminal of the second reset transistor is coupled to the second storage node and wherein the second source-drain terminal of the first reset transistor is coupled to the floating diffusion region.

8. The imaging pixel defined in claim 7 further comprising:

a first transfer transistor coupled between the photosensor and the second storage node; and

a second transfer transistor coupled between the second storage node and the first storage node.