Power management method for a multi-microprocessor system
View Patent ↗A power management method for a multi-microprocessor system is provided. The multi-microprocessor system comprises a first microprocessor and a second microprocessor. The power management method comprises steps of receiving a power down instruction; transmitting a power down notice signal to the first microprocessor from the second microprocessor, transmitting a reply signal from the first microprocessor to the second microprocessor in response to the power down notice signal, and turning off power of the first microprocessor by the second microprocessor.
1. A power management method for a multi-microprocessor system which comprises a first microprocessor, a second microprocessor, and a plurality of function units for performing a plurality of predetermined functions, respectively, the plurality of function units being controlled by the first microprocessor and second microprocessor, comprising the steps of:
receiving a power down instruction indicating the multi-microprocessor system being going to enter a standby state;
transmitting a power down notice signal from the second microprocessor to the first microprocessor;
transmitting a reply signal from the first microprocessor to the second microprocessor in response to the power down notice signal;
turning off power of the first microprocessor by the second microprocessor; and
reducing an operating clock frequency of the second microprocessor when the multi-microprocessor system enters the standby state.
2. The power management method as claimed in claim 1 , further comprising the step of:
turning off the function units.
3. The power management method as claimed in claim 1 , wherein the plurality of function units comprise a video processing unit and an audio processing unit.
4. The power management method as claimed in claim 2 , wherein the multi-microprocessor system further comprises a user interface, which is not turned off when the multi-microprocessor system is in a standby state.
5. The power management method as claimed in claim 1 , wherein the power down instruction is generated when the multi-microprocessor system doesn't receive an input signal within a predetermine time period.
6. The power management method as claimed in claim 1 , wherein the power down instruction is received from a user control device.
7. The power management method as claimed in claim 6 , wherein, when the first microprocessor is turned off, the second microprocessor receives the power down instruction from the user control device via a user interface.
8. The power management method as claimed in claim 1 , wherein, the first microprocessor's processing speed is higher than the second microprocessor's processing speed.