IP Library Granted Patent US 8,093,710
Granted Patent B2
US 8,093,710 · App. 11/694,725 · Granted Jan 10, 2012

Non-uniform feedthrough and lead configuration for a transistor outline package

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Quick Facts
Patent No.
US 8,093,710
App. No.
11/694,725
Granted
Jan 10, 2012
Kind
B2
Abstract

A transistor outline package having a feedthrough via and lead configuration that maximizes the amount of usable area on a header of the package is disclosed. In one embodiment, the package includes a header having an interior surface that includes a first and second lead assembly. The first lead assembly includes two vias having a first diameter, with each first via being positioned along a first pin circle imaginarily defined on the interior surface of the header. Each first via also includes first leads received therein. The second lead assembly includes four vias having a second diameter each, with each second via being positioned along a second pin circle that has a diameter greater than that of the first pin circle. Each second via includes second leads received therein. This configuration increases usable area on the header interior surface between the leads, enabling relatively larger submounts to be placed thereon.

Claims (41)

1. A header assembly for use in an optoelectronic package, comprising:

a header having an interior surface and an exterior surface formed opposite to the interior surface, the header including:

a first lead assembly having:

a plurality of first vias each defined through the header so as to extend from the interior surface to the exterior surface, each of the first vias having a first diameter, each first via being centered on a first pin circle on the interior surface of the header, the first pin circle having a first diameter;

a plurality of first leads, each first lead received by a respective one of the first vias; and

a second lead assembly having:

a plurality of second vias each defined through the header so as to extend from the interior surface to the exterior surface, each of the second vias having a second diameter, each second via being centered on a second pin circle on the interior surface of the header, the second pin circle having a second diameter that is greater than the first diameter of the first pin circle; and

a plurality of second leads, each second lead received by a respective one of the second vias.

2. The header assembly as defined in claim 1 , further comprising a submount that is positioned on the interior surface of the header at least partially within the first and second pin circles.

3. The header assembly as defined in claim 1 , wherein the first and second vias are arranged in a circular pattern.

4. The header assembly as defined in claim 1 , wherein the first lead assembly includes two leads, and wherein the second lead assembly includes four leads.

5. The header assembly as defined in claim 1 , wherein the first leads of the first lead assembly are high speed lines, and wherein the second leads of the second lead assembly are low speed lines.

6. The header assembly as defined in claim 1 , wherein the first and second pin circles are centered about a center of the interior surface.

7. The header assembly as defined in claim 1 , wherein the first diameter of the first vias is greater than the second diameter of the second vias.

8. An optical transceiver module, comprising:

a housing;

a receiver optical subassembly positioned in the housing; and

a transmitter optical subassembly also positioned in the housing and including a transistor outline package, the transistor outline package including:

a header defining a substantially circular outer perimeter and including an interior surface on which a submount is positioned and an exterior surface formed opposite to the interior surface;

a first lead assembly having:

a plurality of first vias each defined through the header so as to extend from the interior surface to the exterior surface, each of the first vias spaced a first distance from the header outer perimeter, each of the first vias having a first diameter; and

a plurality of first leads, each first lead centrally positioned in a respective

one of the first vias;

a second lead assembly having:

a plurality of second vias each defined through the header so as to extend from the interior surface to the exterior surface, each of the second vias spaced the first distance from the header outer perimeter, each of the second vias having a second diameter that is less than the first diameter of the first vias; and

a plurality of second leads, each second lead centrally positioned in a respective one of the second vias.

9. The optical transceiver module as defined in claim 8 , wherein each of the first leads is positioned along a first pin circle of the interior surface of the header, the first pin circle having a first diameter; and wherein each of the second leads is positioned along a second pin circle of the interior surface of the header, the second pin circle having a second diameter that is greater than the first diameter of the first pin circle.

10. The optical transceiver module as defined in claim 8 , wherein the first and second pin circles are imaginarily defined on the interior surface of the header.

11. The optical transceiver module as defined in claim 8 , wherein each of the first and second vias is spaced a second distance from an annular welding point defined on the interior surface of the header.

12. The optical transceiver module as defined in claim 11 , wherein the annular welding point defines a point of contact between the interior surface of the header and a can that attaches to the header, and wherein the first and second vias are sufficiently spaced away from the annular welding point so as to prevent damage to a plurality of glass seals disposed about a portion of each lead received by the respective via.

13. The optical transceiver module as defined in claim 8 , wherein the diameter of each of the first leads is smaller than the diameter of each of the second leads, and wherein the first leads are configured to have an impedance of about 50 ohms.

14. A method of manufacturing a header assembly for use in an optoelectronic package, comprising:

providing a header having an interior surface so as to extend from the interior surface to the exterior surface;

producing a plurality of first vias in the header, each first via defined through the header so as to extend from the interior surface to the exterior surface, each of the first vias having a first diameter, each first via being centered on a first pin circle on the interior surface of the header, the first pin circle having a first diameter selected based on the first diameter of the first vias;

providing a plurality of first leads, each first lead being received by a respective one of the first vias;

producing a plurality of second vias, each second via defined through the header so as to extend from the interior surface to the exterior surface, each of the second vias having a second diameter, each second via being centered on a second pin circle on the interior surface of the header, the second pin circle having a second diameter that is greater than the first diameter of the first pin circle and selected based on the second diameter of the second vias; and

providing a plurality of second leads, each second lead being received by a respective one of the second vias.

15. The method of claim 14 , further comprising selecting a submount and mounting the submount to the inner surface, wherein the size of the submount is selected based on the placement of the first and second vias.

16. The method of claim 15 , wherein the size of the submount is greater than that that would be used where the first and second vias are disposed around the same pin circle.

17. The method of claim 14 , wherein an outer edge of the first and second vias are arranged to tangentially contact a tangent circle thereby placing the outer edge of the first and second vias equidistant from an header outer perimeter.

18. The method of claim 17 , further comprising welding a can to the header, wherein the equidistance of the first and second vias is selected to prevent damage to the first and second vias by the welding process while maximizing the amount of usable area that defines an inner mounting surface for a submount.

Assignments (5)
PATENT RELEASE AND REASSIGNMENT Recorded Jul 5, 2022
From: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
To: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
Reel/Frame 060574/0001 →
SECURITY INTEREST Recorded Jul 1, 2022
From: II-VI INCORPORATED; II-VI DELAWARE, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; PHOTOP TECHNOLOGIES, INC.; COHERENT, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 060562/0254 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2020
From: FINISAR CORPORATION
To: II-VI DELAWARE, INC.
Reel/Frame 052286/0001 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Sep 25, 2019
From: II-VI INCORPORATED; MARLOW INDUSTRIES, INC.; EPIWORKS, INC.; LIGHTSMYTH TECHNOLOGIES, INC.; KAILIGHT PHOTONICS, INC.; COADNA PHOTONICS, INC.; OPTIUM CORPORATION; FINISAR CORPORATION; II-VI OPTICAL SYSTEMS, INC.; M CUBED TECHNOLOGIES, INC.; II-VI PHOTONICS (US), INC.; II-VI DELAWARE, INC.; II-VI OPTOELECTRONIC DEVICES, INC.; PHOTOP TECHNOLOGIES, INC.
To: BANK OF AMERICA, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 050484/0204 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 5, 2007
From: TOGAMI, CHRIS; DOUMA, DARIN J.
To: FINISAR CORPORATION
Reel/Frame 019384/0356 →