Granted Patent B2

US 8,093,929 · App. 12/715,396 · Granted Jan 10, 2012

Abstract

Claims (30)

1. A programmable digital clock signal frequency divider module with a module clock input, module clock output, a scaling factor input, two programming inputs and a tertiary input, the programmable digital clock signal frequency divider comprising:

a primary divider module that includes a first primary module latch circuit with an input coupled to a first one of the programming inputs, a second primary module latch circuit with an input coupled to a second one of the programming inputs, and a third primary module latch circuit with an input coupled to the scaling factor input, wherein an output of the third primary module latch circuit provides a primary divider module output, and wherein the module clock input is coupled to clock inputs of the first, second and third primary module latch circuits; and

a secondary divider module that includes a multiplexer and a divide by two latch, wherein the divide by two latch has a latch clock input coupled to the primary divider module output, and wherein the multiplexer that has a multiplexer output that provides the module clock output, a multiplexer control input coupled to the tertiary input, a first multiplexer data input coupled to an output of the divide by two latch and a second multiplexer data input coupled to the primary divider module output,

wherein in operation the scaling factor input and the two programming inputs control a transfer of data between the first, second and third primary module latch circuits resulting in the primary divider module processing a first sequence of cycles of a primary digital clock signal with a primary digital clock signal period, supplied to the module clock input, into a first base clock signal with a first base clock signal period of at least twice the primary digital clock signal period and processing a subsequent second sequence of cycles of the primary digital clock signal into a second base clock signal with a second base clock signal period of at least twice the primary digital clock signal period, and wherein the first and second base clock signals provide a sequence of clock pulses to the secondary divider module, and edges of the sequence of clock pulses trigger the divide by two latch resulting in a latch output clock signal with a 50% duty cycle at the output of the divide by two latch, and wherein the tertiary input selects one of the sequence of clock pulses and the latch output clock signal to be a module clock output signal at the module clock output.

2. The programmable digital clock signal frequency divider module of claim 1 , wherein an output of the second primary module latch circuit is coupled to an input of the third primary module latch circuit and selectively connectable to an input of the first primary module latch circuit, and an output of the first primary module latch circuit is coupled to both an input of the second primary module latch circuit and an input of the third primary module latch circuit, and wherein the output of the third primary module latch circuit is coupled to an input of the second primary module latch circuit.

3. The programmable digital clock signal frequency divider module of claim 1 , wherein the latch output clock signal has a clock period that is twice a period of the first base clock signal.

4. The programmable digital clock signal frequency divider module of claim 3 , wherein the first base clock signal period is twice the primary digital clock signal period and the second base clock period is twice the primary digital clock signal period.

5. The programmable digital clock signal frequency divider module of claim 3 , wherein the first base clock signal period is twice the primary digital clock signal period and the second base clock period is three times the primary digital clock signal period.

6. The programmable digital clock signal frequency divider module of claim 3 , wherein the first base clock signal period is three times the primary digital clock signal period and the second base clock period is three times the primary digital clock signal period.

7. The programmable digital clock signal frequency divider module of claim 3 , wherein the first base clock signal period is three times the primary digital clock signal period and the second base clock period is four times the primary digital clock signal period.

8. The programmable digital clock signal frequency divider module of claim 7 , wherein in operation the first and second primary module latch circuits are programmable by the two programming inputs to process the first and second sequences of cycles into the first base clock signal and the second base clock signal, and the third primary module latch circuit is programmable by the two programming inputs to delay the sequence of clock pulses at the latch clock input of the secondary divider module by at least one cycle of the primary digital clock signal.

9. The programmable digital clock signal frequency divider module of claim 8 , wherein in operation the scaling factor input provides a scaling factor input signal that blocks transfer of data from the second primary module latch circuit to the third primary module latch circuit.

10. The programmable digital clock signal frequency divider module of claim 9 , wherein in operation when the scaling factor signal allows the transfer of data from the second primary module latch circuit to the third primary module latch circuit, logic values applied to the two programming inputs and the tertiary input determine an output signal period of the module clock output signal.

11. The programmable digital clock signal frequency divider module of claim 10 , wherein when the scaling factor signal allows the transfer of data from the output of the second primary module to the primary divider module output, the output signal period is selected from the group of: twice the primary digital clock signal period; three times the primary digital clock signal period; four times the primary digital clock signal period; five times the primary digital clock signal period; six times the primary digital clock signal period; and seven times the primary digital clock signal period.

12. The programmable digital clock signal frequency divider module of claim 1 , further including a scaling factor output that provides a pulsed signal comprising identical spaced pulses of a pulse width equal to the primary digital clock signal period.

13. The programmable digital clock signal frequency divider module of claim 1 , further including a tertiary clock output that provides a clocking signal CLK, wherein during the first sequence of cycles the clocking signal CLK has a period that is at least twice that of the primary digital clock signal period.

14. A modular digital clock signal frequency divider circuit for dividing a system clock signal, the modular digital clock signal frequency divider circuit comprising a plurality of series connected programmable digital clock signal frequency divider modules, wherein one of the modules is an output stage module with a module clock input, module clock output, a scaling factor input, two programming inputs and one tertiary input, the output stage module comprising:

a primary divider module that includes a first primary module latch circuit with an input coupled to a first one of the programming inputs, a second primary module latch circuit with an input coupled to a second one of the programming inputs, a third primary module latch circuit with an input coupled to the scaling factor input, wherein an output of the third primary module latch circuit provides a primary divider module output, and wherein the module clock input is coupled to clock inputs of the first, second and third primary module latch circuits; and

a secondary divider module that includes a multiplexer and a divide by two latch with a latch clock input coupled to the primary divider module output, the multiplexer has a multiplexer output, that provides the module clock output, a multiplexer control input coupled to the tertiary input, a first multiplexer data input coupled to an output of the divide by two latch and a second multiplexer data input coupled to the primary divider module output,

wherein in operation, logic values applied to the scaling factor input and the programming inputs control transfer of data between the first, second and third primary module latch circuits resulting in the primary divider module processing a first sequence of cycles of a primary digital clock signal with a primary digital clock signal period, supplied to the module clock input, into a first base clock signal with a first base clock signal period of at least twice the primary digital clock signal period and processing a subsequent second sequence of cycles of the primary digital clock signal into a second base clock signal with a second base clock signal period of at least twice the primary digital clock signal period, and wherein the first base clock signal and the second base clock signal provide a sequence of clock pulses to the secondary divider module, and edges of the sequence of clock pulses trigger the divide by two latch thereby resulting in a latch output clock signal with a 50% duty cycle at the output of the divide by two latch, and wherein logic values at the tertiary input select one of the sequence of clock pulses and the latch output clock signal to be a module clock output signal at the module clock output.

15. The modular digital clock signal frequency divider circuit of claim 14 , wherein in operation, the scaling factor input provides a scaling factor signal that blocks the sequence of clock pulses from being supplied to the secondary divider module clock input.

16. The modular digital clock signal frequency divider circuit of claim 14 , wherein in operation, signals applied to the scaling factor input and logic values applied to the programming inputs determine a clock output signal period of an output signal of the multiplexer.

17. The modular digital clock signal frequency divider circuit of claim 16 , wherein the clock output signal period=

(2 n-1 ×MODn−1+2 n-2 ×MODn−2+ . . . 2×MOD1+MOD0)×Tin,

where Tin is a period of the system clock signal, n−2 is the number of modules in the circuit, and MOD 0 to MODn are binary values that are selectively applied to a programming input of a respective module of the modular digital clock signal frequency divider circuit.

18. The modular digital clock signal frequency divider circuit of claim 16 , wherein the output signal period=

(2 n-1 ×MODn−1+2 n-2 ×MODn−2+ . . . MOD1+0.5×MOD0)×Tin,

where Tin is a period of the system clock signal, n−2 is the number of modules in the circuit, and MOD 0 to MODn are binary values selectively applied to a programming input of a respective module of the modular digital clock signal frequency divider circuit.

19. The modular digital clock signal frequency divider circuit of claim 14 , wherein the output stage module further includes a scaling factor output that provides a pulsed signal comprising identical spaced pulses of a pulse width equal to the primary digital clock signal period.

20. The modular digital clock signal frequency divider circuit of claim 14 , wherein the output stage module further includes a tertiary clock output that provides a clocking signal, and wherein during the first sequence of cycles the clocking signal has period that is at least twice that of the primary digital clock signal period.

Assignments (33)