CCD array with integrated high voltage protection circuit
A CCD containing circuit and method for making the same. The circuit includes a CCD array and a protection circuit. The CCD array is constructed on an integrated circuit substrate and includes a plurality of gate electrodes that are insulated from the substrate by an insulating layer. The gate electrodes are connected to a conductor bonded to the substrate. The protection circuit is also constructed on the substrate. The protection circuit is connected to the conductor and to the substrate and protects the CCD array from both negative and positive voltage swings generated by electrostatic discharge events and the like. The protection circuit and the CCD can be constructed in the same integrated circuit fabrication process.
1. A method for fabricating a CCD device on a substrate comprising:
fabricating a CCD array and a protection circuit on said substrate using the same fabrication process, said CCD array comprising a plurality of gate electrodes that are connected to said protection device by a conductor, said protection circuit being connected to said conductor and to said substrate, said protection circuit having a first state in which said protection circuit provides an impedance greater than an operating impedance between said conductor and said substrate and a second state in which said protection circuit provides a shorting impedance between said conductor and said substrate, said protection circuit being in said first state if the potential on said conductor is in an operating range defined by a negative threshold potential and a positive threshold potential, and said protection circuit being in said second state if said potential on said conductor is outside said operating range; and
connecting said gate electrodes to said protection circuit by a metal layer.
2. The method of claim 1 wherein said process comprises a PMOS process and wherein said protection circuit comprises an NPN bipolar transistor and a PNP bipolar transistor with its base shorted to ground.
3. The method of claim 1 wherein said process comprises an NMOS process and wherein said protection circuit comprises a PNP bipolar transistor and an NPN bipolar transistor with its base shorted to ground.