IP Library Granted Patent US 8,106,495
Granted Patent B2
US 8,106,495 · App. 12/639,421 · Granted Jan 31, 2012

Semiconductor apparatus and manufacturing method thereof

Assignee: Shinko Electric Industries Co., Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,106,495
App. No.
12/639,421
Granted
Jan 31, 2012
Kind
B2
Abstract

A semiconductor apparatus includes a first wiring substrate, a second wiring substrate, a semiconductor chip, an adhesive layer and a molding resin. The second wiring substrate is stacked and connected on the first wiring substrate through a bump electrode. The semiconductor chip is mounted on the first wiring substrate by flip chip bonding and received between the first wiring substrate and the second wiring substrate. An upper surface of the semiconductor chip is subject to a mirror treatment. The adhesive layer is formed on the upper surface of the semiconductor chip. The molding resin is filled in a gap between the first wiring substrate and the second wiring substrate.

Claims (12)

1. A semiconductor apparatus comprising:

a first wiring substrate;

a second wiring substrate which is stacked and directly connected to on the first wiring substrate through a bump electrode;

a semiconductor chip which is mounted on the first wiring substrate by flip chip bonding and received between the first wiring substrate and the second wiring substrate, an upper surface of the semiconductor chip being formed as a mirror surface;

an adhesive layer which is formed on the upper surface of the semiconductor chip; and

a molding resin which is filled in a gap between the first wiring substrate and the second wiring substrate,

wherein the molding resin is interposed between an upper surface of the adhesive layer on the semiconductor chip and a lower surface of the second wiring substrate, and the molding resin is directly adhered to the upper surface of the adhesive layer.

2. A semiconductor apparatus as claimed in claim 1 , wherein the adhesive layer is formed of a coupling material or a resin without including a mold release material and the molding resin includes a mold release material.

3. A semiconductor apparatus as claimed in claim 1 , further comprising:

an under fill resin which fills in a gap between a lower side of the semiconductor chip and an upper surface of the first wiring substrate,

wherein the adhesive layer is made of the same resin as the under fill resin.

4. A semiconductor apparatus as claimed in claim 1 , wherein the mirror surface has a surface roughness Ra, wherein 8 μm≦Ra≦12 μm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 16, 2009
From: KAJIKI, ATSUNORI
To: SHINKO ELECTRIC INDUSTRIES CO., LTD.
Reel/Frame 023663/0542 →
Priority Claims (1)
JP 2008-321038 · Dec 17, 2008 · national
Continuity (1)
Related Publication 20100148332A1 · Jun 17, 2010