Equalization in capacitively coupled communication links

1. An integrated circuit containing a communication channel, wherein the communication channel comprises:

a transmit circuit configured to transmit signals using a voltage-mode driver;

a capacitive link coupled to the transmit circuit;

a receive circuit, wherein the transmit circuit is capacitively coupled to the receive circuit via the capacitive link;

a filter to equalize signals communicated between the transmit circuit and the receive circuit, wherein the filter includes a capacitive-summing junction; and

one or more taps in the filter, wherein an output voltage of the filter is a weighted average of voltages for taps in the filter, and wherein a weight for each voltage is proportional to a capacitance for the corresponding tap relative to a capacitance for the capacitive link, wherein the filter includes at least one tap with a weight element that has an adjustable weight, wherein adjusting the adjustable weight of the weight element involves adjusting a capacitance of the weight element, wherein a relationship between a control voltage input to the weight element and the capacitance of the weight element is non-linear.

2. The integrated circuit of claim 1 , wherein the filter is included in the transmit circuit.

3. The integrated circuit of claim 1 , wherein the filter is included in the receive circuit.

4. The integrated circuit of claim 1 , wherein the filter is configured to reduce cross-talk between at least two signal lines in the link.

5. The integrated circuit of claim 1 , wherein a frequency response for the link and the filter is approximately uniform over a range of frequencies.

6. The integrated circuit of claim 1 , wherein the filter includes a finite impulse response (FIR) filter.

7. The integrated circuit of claim 1 , wherein the capacitive-summing junction includes at least two signal lines that are proximate to one another.

8. The integrated circuit of claim 1 , further including control logic, wherein the control logic is configured to adjust a frequency response of the filter in accordance with a performance metric of the communication channel.

9. The integrated circuit of claim 8 , wherein the control logic is configured to adjust the frequency response when the integrated circuit is powered on.

10. The integrated circuit of claim 8 , wherein the control logic is configured to adjust the frequency response after at least a pre-determined time interval since a last adjustment.

11. The integrated circuit of claim 8 , wherein the control logic is configured to adjust the frequency response continuously.

12. The integrated circuit of claim 8 , wherein the performance metric includes a difference between a sequence received by the receive circuit and a pre-determined sequence.

13. The integrated circuit of claim 1 , wherein the filter includes delay elements that have discrete time delays.

14. The integrated circuit of claim 13 , wherein the delay elements are configured to be clocked using a clock signal that has a frequency that is different from a chip rate of the integrated circuit.

15. The integrated circuit of claim 1 , wherein the filter includes delay elements that have continuous time delays.

16. The integrated circuit of claim 1 , wherein a capacitance of a respective weight element corresponds to a number of capacitances that are selectively coupled to an input and an output of the respective weight element.

17. A computer system, comprising:

a processor;

memory, wherein the memory is configured to store one or more program module mechanisms; and

an integrated circuit containing a communication channel, wherein the communication channel includes:

a transmit circuit configured to transmit signals using a voltage-mode driver;

a capacitive link coupled to the transmit circuit;

a receive circuit, wherein the transmit circuit is capacitively coupled to the receive circuit via the capacitive link;

a filter to equalize signals communicated between the transmit circuit and the receive circuit, wherein the filter includes a capacitive-summing junction; and

one or more taps in the filter, wherein an output voltage of the filter is a weighted average of voltages for taps in the filter, and wherein a weight for each voltage is proportional to a capacitance for the corresponding tap relative to a capacitance for the capacitive link, wherein the filter includes at least one tap with a weight element that has an adjustable weight, wherein adjusting the adjustable weight of the weight element involves adjusting a capacitance of the weight element, wherein a relationship between a control voltage input to the weight element and the capacitance of the weight element is non-linear.

18. A method of communicating signals within an integrated circuit, comprising:

communicating signals from a transmit circuit through a capacitive link to a receive circuit, wherein the signals are communicated using voltage-mode signaling;

as the signals are communicated, equalizing the signals using a filter that includes a capacitive-summing junction and one or more taps, wherein an output voltage of the filter is a weighted average of voltages for taps in the filter, and wherein a weight for each voltage is proportional to a capacitance for the corresponding tap relative to a capacitance for the capacitive link, wherein the filter includes at least one tap with a weight element that has an adjustable weight, wherein adjusting the adjustable weight of the weight element involves adjusting a capacitance of the weight element, wherein a relationship between a control voltage input to the weight element and the capacitance of the weight element is non-linear.

19. The integrated circuit of claim 1 , further comprising control logic configured to adjust the capacitance for one or more taps.