Block specific harmonic balance analysis system
View Patent ↗This invention is directed to a circuit simulation using multi-rate harmonic balancing. Specifically, this invention enables effective reduction of analysis dimensions, e.g. frequency or time. The methodology converts N-dimensional problems to local (N-x)-dimensional problems. The method enables simultaneous solving of all local problems, each of these problems having a dimension less than or equal to N, thus approximating the original system to be solved. In practical situations, N could be the number of independent frequencies in an N-tone harmonic balance analysis.
1. A method for obtaining steady state values of a circuit design, comprising:
utilizing a computer to perform:
automatically identifying a plurality of circuit blocks in the circuit design;
selecting at least a subset of the plurality of circuit blocks;
generating circuit equations based on the selected subset, wherein the circuit equations comprise at least one non-linear equation;
for a first circuit block of the subset, specifying a first set of frequencies;
for a second circuit block of the subset, specifying a second set of frequencies, wherein the first set of frequencies differs from the second set of frequencies by at least one frequency;
solving the circuit equations for the first and second set of frequencies to obtain at least one steady state value.
2. The method of claim 1 , wherein said generating the circuit equations based on the selected subset comprises generating a first set of equations for the first circuit block of the subset and generating a second set of equations for the second circuit block of the subset, wherein the first set of equations is different from the second set of equations.
3. The method of claim 1 , wherein said selecting the at least the subset of the plurality of circuit blocks is performed in response to user input.
4. The method of claim 1 , further comprising:
utilizing the computer to perform:
refining the at least a subset of circuit blocks, wherein said refining is performed by trading off speed of said solving the circuit equations with memory consumption.
5. The method of claim 1 , wherein the at least one steady state value is for current.
6. The method of claim 1 , wherein the at least one steady state value is for voltage.
7. The method of claim 1 , wherein the at least one steady state value is for power.
8. The method of claim 1 , wherein said solving the circuit equations produces a Jacobian matrix that includes information on current derivatives at the location of at least one node in the circuit design.
9. The method of claim 1 , further comprising:
utilizing the computer to perform:
multiplying nonlinear parameters of a block's characteristics to describe a block.
10. The method of claim 1 , wherein said selecting the at least a subset of the plurality of circuit blocks comprises using a frequency selection tool.
11. The method of claim 1 , wherein said selecting the at least a subset of the plurality of circuit blocks comprises selecting initial values in response to user input.
12. The method of claim 1 , wherein said selecting the at least a subset of the plurality of circuit blocks comprises selecting initial values by using a result from a previous simulation.
13. The method of claim 1 , wherein said selecting the at least a subset of the plurality of circuit blocks is performed automatically based on error estimation during an iterative process.
14. The method of claim 1 , wherein said selecting the at least a subset of the plurality of circuit blocks comprises selecting initial values by oversampling nonlinear elements of at least one desired frequency.
15. The method of claim 14 , further comprising:
utilizing the computer to perform:
using harmonic balance to select the at least one desired frequency.
16. The method of claim 14 , further comprising:
utilizing the computer to perform:
using frequency domain steady state to select the at least one desired frequency.
17. The method of claim 1 , wherein said specifying the first set of frequencies comprises specifying at least one frequency harmonic.
18. The method of claim 16 , wherein said specifying the at least one frequency harmonic comprises using a box truncation.
19. The method of claim 17 , wherein said specifying the at least one frequency harmonic comprises using a diamond truncation.
20. The method of claim 17 , wherein said specifying the at least one frequency harmonic comprises using numerical estimation of subsequent reduction of equation error.
21. A non-transitory, computer-accessible memory medium storing program instructions for obtaining steady state values of a circuit design, wherein the program instructions are executable to:
automatically identify a plurality of circuit blocks in the circuit design;
select at least a subset of the plurality of circuit blocks;
generate circuit equations based on the selected subset, wherein the circuit equations comprise at least one non-linear equation;
for a first circuit block of the subset, specify a first set of frequencies;
for a second circuit block of the subset, specify a second set of frequencies, wherein the first set of frequencies differs from the second set of frequencies by at least one frequency;
solve the circuit equations for the first and second set of frequencies to obtain at least one steady state value.
22. The non-transitory, computer accessible memory medium of claim 21 , wherein said generating the circuit equations based on the selected subset comprises generating a first set of equations for the first circuit block of the subset and generating a second set of equations for the second circuit block of the subset, wherein the first set of equations is different from the second set of equations.
23. The non-transitory, computer accessible memory medium of claim 21 , wherein said selecting the at least the subset of the plurality of circuit blocks is performed in response to user input.
24. The non-transitory, computer accessible memory medium of claim 21 , wherein the at least one steady state value is for current.
25. The non-transitory, computer accessible memory medium of claim 21 , wherein the at least one steady state value is for voltage.
26. The non-transitory, computer accessible memory medium of claim 21 , wherein the at least one steady state value is for power.
27. The non-transitory, computer accessible memory medium of claim 21 , wherein said solving the circuit equations produces a Jacobian matrix that includes information on current derivatives at the location of at least one node in the circuit design.
28. The non-transitory, computer accessible memory medium of claim 21 , wherein said selecting the at least a subset of the plurality of circuit blocks comprises selecting initial values in response to user input.
29. The non-transitory, computer accessible memory medium of claim 21 , wherein said selecting the at least a subset of the plurality of circuit blocks comprises selecting initial values by using a result from a previous simulation.
30. The non-transitory, computer accessible memory medium of claim 21 , wherein said selecting the at least a subset of the plurality of circuit blocks comprises selecting initial values by oversampling nonlinear elements of at least one desired frequency.
31. The non-transitory, computer accessible memory medium of claim 21 , wherein said specifying the first set of frequencies comprises specifying at least one frequency harmonic.
32. The non-transitory, computer accessible memory medium of claim 31 , wherein said specifying the at least one frequency harmonic comprises using a box truncation.
33. The non-transitory, computer accessible memory medium of claim 31 , wherein said specifying the at least one frequency harmonic comprises using a diamond truncation.