IP Library Granted Patent US 8,174,872
Granted Patent B2
US 8,174,872 · App. 12/746,589 · Granted May 8, 2012

Nonvolatile latch circuit

Assignee: NEC Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,174,872
App. No.
12/746,589
Granted
May 8, 2012
Kind
B2
Abstract

A nonvolatile latch circuit includes: first and second inverters cross-coupled to hold 1-bit data; first and second magnetoresistive elements each having first to third terminals; and a current supply circuitry configured to supply a magnetization reversal current for changing the magnetization states of the first and second maqnetoresistive elements in response to the 1-bit data. The power terminal of the first inverter is connected to the first terminal of the first magnetoresistive element and the power terminal of the second inverter is connected to the first terminal of the second magnetoresistive element. The current supply circuitry is configured to supply the magnetization reversal current to the second terminals of the first and second magnetoresistive elements. The third terminal of the first magnetoresistive element is electrically connected to the third terminal of the second magnetoresistive element.

Claims (24)

1. A nonvolatile latch circuit, comprising:

first and second inverters cross-coupled to hold 1-bit data;

first and second magnetoresistive elements each having first to third terminals; and

a current supply circuitry configured to supply a magnetization reversal current for changing magnetization states of said first and second magnetoresistive elements in response to said 1-bit data,

wherein a power terminal of said first inverter is connected to said first terminal of said first magnetoresistive element,

wherein a power terminal of said second inverter is connected to said first terminal of said second magnetoresistive element,

wherein said current supply circuitry is configured to supply said magnetization reversal current to said second terminals of said first and second magnetoresistive elements, and

wherein said third terminal of said first magnetoresistive element is electrically connected to said third terminal of said second magnetoresistive element.

2. The nonvolatile latch circuit according to claim 1 , wherein each of said first and second magnetoresistive elements are configured so that a tunnel current flows through a magnetic tunnel junction between said first and second terminals, and said magnetization reversal current flows between said second and third terminals.

3. The nonvolatile latch circuit according to claim 1 , further comprising:

a first switch which electrically connects and disconnects outputs of said first and second inverters.

4. The nonvolatile latch circuit according to claim 1 , wherein said current supply circuitry is configured to supply complementary voltages to said second terminals of said first and second magnetoresistive elements in response to voltage levels of the outputs of said first and second inverters.

5. The nonvolatile latch circuit according to claim 1 , further comprising:

a second switch which supplies input data to an input of said first inverter in response to a clock signal; and

a third switch which supplies inverted data of said input data to an input of said second inverter in response to said clock signal.

6. The nonvolatile latch circuit according to claim 1 , wherein said current supply circuitry has first and second input terminals and first and second output terminals,

wherein said first input terminal is connected to the output of said first inverter and said second input terminal is connected to the output of said second inverter, and

wherein said first output terminal is connected to said second terminal of said first magnetoresistive element and said second output terminal is connected to said second terminal of said second magnetoresistive element.

7. The nonvolatile latch circuit according to claim 1 , wherein said current supply circuitry has first and second input terminals and first and second output terminals,

wherein said first input terminal is connected to the output of said first inverter and said second input terminal is connected to the output of said second inverter, and

wherein said first output terminal is connected to said second terminal of said second magnetoresistive element and said second output terminal is connected to said second terminal of said first magnetoresistive element.

8. The nonvolatile latch circuit according to claim 1 , wherein said current supply circuitry has first and second input terminals and first and second output terminals,

wherein said first input terminal is connected to the output of said second inverter and said second input terminal is connected to the output of said first inverter, and

wherein said first output terminal is connected to said second terminal of said first magnetoresistive element and said second output terminal is connected to said second terminal of said second magnetoresistive element.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 7, 2010
From: SAKIMURA, NOBORU; SUGIBAYASHI, TADAHIKO; NEBASHI, RYUSUKE
To: NEC CORPORATION
Reel/Frame 024646/0450 →
Priority Claims (1)
JP 2007-316397 · Dec 6, 2007 · national
Continuity (1)
Related Publication 20100271866A1 · Oct 28, 2010