Integrated circuit device and electronic apparatus

1. An integrated circuit device comprising:

an internal circuit;

a ground terminal;

a first terminal that is provided with a first signal that becomes to be a ground level during at least a portion of a period in which the internal circuit is operating, the first terminal being a clock terminal that receives a clock signal as the first signal;

a detection circuit that compares a voltage on the first terminal and a voltage on the ground terminal, thereby detecting an open state of the ground terminal; and

a setting circuit that sets the internal circuit to a reset state or a disabled state when the open state of the ground terminal is detected by the detection circuit.

2. An integrated circuit device according to claim 1 , further comprising:

a second terminal and an I/O cell that receives a second signal inputted through the second terminal,

wherein the I/O cell includes an electrostatic protection element provided between the second terminal and the ground, and the second signal is a signal that becomes a ground level for at least a part of a period in which the internal circuit operates.

3. An integrated circuit device according to claim 1 , wherein the detection circuit includes a voltage comparator circuit having

a first transistor of a first conductivity type having a control node that receives a voltage on the first terminal,

a second transistor of the first conductivity type having a control node that receives a voltage on the ground terminal and forming a differential pair with the first transistor,

a current mirror circuit that is a load of the differential pair composed of the first transistor and the second transistor, and

a third transistor as a current source transistor that supplies an operation current to the differential pair and the current mirror circuit.

4. An electronic apparatus that includes the integrated circuit device recited in claim 1 .

5. An integrated circuit device according to claim 1 , wherein the setting circuit has a latch circuit that retains the level of an operation state control signal for setting the internal circuit to a reset state or a disabled state upon detection of the open state of the ground terminal by the detection circuit to an active level in a period in which the internal circuit is in an enabled state.

6. An integrated circuit device according to claim 5 ,

further comprising an enable terminal for inputting an enable signal for switching between enabling and disabling the internal circuit,

wherein, when the enable signal changes from an active level to a non-active level thereby changing the internal circuit from an enabled state to a disabled state, the latch circuit is also reset.