Performance in a virtualization architecture with a processor abstraction layer

1. An apparatus comprising:

a processor;

a processor abstraction layer (“PAL”) including PAL procedure instructions, accessible to the processor as a PAL procedure with a decode operation to determine a first function to be performed with a parameter checking operation and with a processor state checking operation, and PAL service instructions, accessible to the processor as a PAL service without a decode operation to determine a second function to be performed without the parameter checking operation and without the processor state checking operation, where the PAL service instructions, when executed by the processor, support at least one technique to improve the performance of the apparatus in a virtualization architecture.

2. The apparatus of claim 1 , wherein the PAL also includes a PAL service jump table.

3. The apparatus of claim 2 , wherein the PAL service jump table includes an offset value, and the PAL service is accessible to the processor by executing an instruction to branch to a memory location addressable as a base address plus the offset value.

4. The apparatus of claim 1 , wherein the processor includes circuitry to support the virtualization of a hardware resource.

5. The apparatus of claim 4 , wherein the circuitry is a shadow register to shadow attempts to access an architectural register.

6. The apparatus of claim 5 , wherein the instructions include synchronization instructions that, when executed by the processor, synchronize the values in the shadow register with the values in a virtual register corresponding to the architectural register.

7. A method comprising:

initializing a virtualization environment in a virtualization architecture;

performing a parameter checking operation in connection with calling a procedure instruction in a processor abstraction layer (“PAL”);

performing a processor state checking operation in connection with calling the procedure instruction;

calling the procedure instruction;

performing a decode operation, in response to calling the procedure instruction, to determine a first function to be performed;

and

calling a service instruction in the PAL without a decode operation to determine a second function to be performed to support at least one technique to improve the performance of software running in the virtualization architecture without the parameter checking operation and without the processor state checking operation.

8. The method of claim 7 further comprising passing a base address of the PAL service to the caller.

9. The method of claim 7 further comprising executing the service instruction to synchronize a hardware resource to support virtualization with a virtual resource.

10. The method of claim 9 wherein the hardware resource is a shadow register and the virtual resource is a virtualized copy of an architectural register.

11. The method of claim 7 further comprising determining whether the service instruction is to be executed based on an indicator.

12. The method of claim 11 wherein the indicator is based on an enable indicator that indicates whether the technique is enabled.

13. The method of claim 11 wherein the indicator is based on a selection indicator that indicates whether the service instruction is selected.