High frame rate high definition imaging system and method
A high frame rate high definition imaging system and method are disclosed. An imager is clocked asynchronously to a desired output video clock. During a frame cycle, data held in a first portion of the pixel array in the imager is clocked out of the imager using an imager clock signal, and data held in a second portion of the pixel array is bypassed. The imager data is subsequently converted to a higher video clock rate and output as desired video data.
1. An imaging system adapted for outputting a video data signal having a video pixel clock rate and a video frame rate, comprising:
a timing generator simultaneously providing an imager pixel clock signal and a video pixel clock signal, the imager pixel clock signal having an imager pixel clock rate and an imager frame rate, and the video pixel clock signal having the video pixel clock rate that is greater than the imager pixel clock rate and the video frame rate that is equal to the imager frame rate;
a standard imager having a nominal clock rate that is lower than the video pixel clock rate of the video data signal, the standard imager having an imager clock input receiving the imager pixel clock signal and a data output which outputs imager data comprising frames of sequential lines of active image data at the imager pixel clock rate; and
a pixel clock rate converter comprised of a memory buffer coupled to the data output of the standard imager, and a memory control circuit for controlling the writing and reading of image data to and from the memory buffer which is coupled to the timing generator and receiving the imager pixel clock signal and the video pixel clock signal, the pixel clock rate converter receiving the imager data from the standard imager synchronously with the imager pixel clock signal and at a rate equal to the imager pixel clock rate, and outputting buffered image data at a rate equal to the video pixel clock rate that is greater than the imager pixel clock rate.
2. The imaging system of claim 1 , wherein the standard imager comprises a pixel array holding pixel data representative of an image captured by the standard imager, the pixel array having a first portion and a second portion.
3. The imaging system of claim 2 , wherein the timing generator generates a sequence of timing signals to control the standard imager to skip over the second portion of the pixel array and clock the first portion of the pixel array from the standard imager to the pixel clock rate converter.
4. The imaging system of claim 3 , wherein the timing generator generates horizontal timing pulses and vertical timing pulses, and wherein the horizontal timing pulses correspond to the imager pixel clock rate.
5. The imaging system of claim 1 , wherein the imager pixel clock signal and the video pixel clock signal are asynchronous to one another.
6. The imaging system of claim 3 , wherein the first portion of the pixel array comprises desired active pixels.
7. The imaging system of claim 6 , wherein the second portion of the pixel array comprises inactive or dummy pixels.
8. The imaging system of claim 3 , wherein the second portion of the pixel array comprises a combination of undesired active pixels and inactive pixels, and the first portion comprises desired active pixels of the pixel array.
9. The imaging system of claim 3 , wherein the standard imager is a CCD sensor and electric charge is accumulated by the standard imager for the pixels of the pixel array, and wherein the electric charge associated with the second portion of the pixel array is shifted out of the standard imager simultaneously for groups of plural rows.
10. The imaging system of claim 9 , wherein one or more horizontal and vertical timing pulses control the accumulation of electric charge in a transfer portion of the standard imager and the horizontal transfer clock controls the transfer of charge corresponding to plural rows of pixel data out of the standard imager simultaneously.
11. The imaging system of claim 1 , wherein the timing generator comprises:
an imager clock generator circuit block outputting an imager clock;
a video clock generator circuit block outputting a video clock;
a master synchronization circuit block; and
an imager timing logic block, coupled to the imager clock generator and master synchronization circuit blocks and outputting said imager pixel clock signal at the imager pixel clock rate.
12. The imaging system of claim 11 , wherein the master synchronization circuit block is coupled to the video clock generator circuit block and receives the video clock.
13. The imaging system of claim 12 , wherein a rate converter control logic comprises video timing logic coupled to the memory control circuit and to the timing generator and receiving the video pixel clock signal, wherein the video timing logic controls the memory control circuit to interrupt read out of the image data from the memory buffer during blanking intervals of an output video data.
14. The imaging system of claim 13 , wherein the rate converter control logic further comprises a video output generator coupled to the memory buffer and the video timing logic, wherein the video output generator receives the output video data from the memory buffer and inserts blanking data during blanking intervals during which the read out of the memory buffer is suspended and outputs video data with actual pixel data and blanking data at the video pixel clock rate.
15. The imaging system of claim 14 , wherein the output video data is provided in a VESA standard timing.
16. The imaging system of claim 14 , wherein the output video data is provided in a SMPTE HDTV standard timing.
17. A method of providing video data having a video pixel clock rate and a video frame rate, comprising:
providing a standard imager having a nominal clock rate that is lower than the video pixel clock rate and an imager frame rate that is equal to the video frame rate;
clocking frames of image data from the standard imager using an imager pixel clock signal at an imager pixel clock rate;
converting the image data with a memory buffer to the video data at the video pixel clock rate simultaneously greater than the imager pixel clock rate, with the imager frame rate being equal to the video frame rate.
18. The method of claim 17 , wherein converting the image data to the video data further comprises writing the image data into the memory buffer at a rate synchronous to the imager pixel clock rate, and reading the image data out of the memory buffer at a different clock rate.
19. The method of claim 18 , wherein converting the image data to the video data further comprises inserting blanking data, corresponding to blanking intervals of the video data, into the image data.
20. The method of claim 19 , wherein converting the image data to the video data further comprises suspending read out of the image data from the memory buffer during said inserting of blanking pixel data.
21. The method of claim 17 , wherein the imager pixel clock signal is asynchronous to the video data.
22. The method of claim 21 , wherein the video data is output in a VESA standard timing.
23. The method of claim 21 , wherein the video data is output in a SMPTE HDTV standard timing.