Clock domain check method, clock domain check program, and recording medium
To reduce pseudo errors, a stationary signal is propagated through the circuit to be checked. A combination is extracted in which different asynchronous transfers occur between a transmitting side register and a receiving side register. From the extracted combination of asynchronous transfers, a circuit to be checked is extracted, and a synchronization circuit of a plurality of signals is excluded from the circuit to be checked. A stationary signal is propagated through the circuit to be checked, for each combination among all combinations of logic values “1” and “0” of the stationary signal. It is checked whether or not there exists one asynchronous transmitting side register to which signal change can logically reach, in the combination of logic values of the stationary signal propagated. Based on the result, it is determined whether or not the circuit is appropriate as a synchronization circuit for a single-signal transfer, thereby reducing pseudo errors.
1. A clock domain check method which performs a clock domain check in a circuit to be checked using a central processing unit, the method comprising:
a first step of allowing a stationary signal defined as a signal whose logic value does not change in an asynchronous transfer to propagate through the circuit to be checked;
a second step of extracting a combination in which different asynchronous transfers occur between a transmitting side register and a receiving side register;
a third step of extracting a circuit to be checked from the combination of asynchronous transfers extracted in the second step by back-tracing for each of the receiving side registers toward the transmitting side and searching the transmitting side register, a circuit that leads to the transmitting side register, and a stationary signal, and excluding a synchronization circuit of a plurality of signals from the circuit to be checked;
a fourth step of allowing a stationary signal for each combination among all combinations of logic values “1” and “0” of the stationary signal to propagate through the circuit to be checked;
a fifth step of checking, from the connection relation, whether or not there exists one asynchronous transmitting side register to which signal change logically reaches, in the combination of logic values of the stationary signal propagated in the fourth step; and
a sixth step of determining, based on the check result in the fifth step, whether or not the circuit configuration relating to asynchronous transfer is appropriate as a synchronization circuit for a single-signal transfer,
wherein the first to sixth steps are executed by the central processing unit.
2. The clock domain check method according to claim 1 ,
wherein the stationary signal is set to a fixed logic value of either “0” or “1” and the logic value does not change when other signals that perform asynchronous crossing in the asynchronous transfer.
3. A clock domain check program which checks a synchronization circuit in asynchronous transfer by causing a computer to execute:
a first procedure of allowing a stationary signal defined as a signal whose logic value does not change in an asynchronous transfer to propagate through the circuit to be checked;
a second procedure of extracting a combination in which different asynchronous transfers occur between a transmitting side register and a receiving side register;
a third procedure of extracting a circuit to be checked from the combination of asynchronous transfers extracted in the second procedure by back-tracing for each of the receiving side registers toward the transmitting side and searching the transmitting side register, a circuit that leads to the transmitting side register, and a stationary signal, and excluding a synchronization circuit of a plurality of signals from the circuit to be checked;
a fourth procedure of allowing a stationary signal for each combination among all combinations of logic values “1” and “0” of the stationary signal to propagate through the circuit to be checked;
a fifth procedure of checking, from the connection relation, whether or not there exists one asynchronous transmitting side register to which signal change logically reaches, in the combination of logic values of the stationary signal propagated in the fourth procedure; and
a sixth procedure of determining, based on the check result in the fifth procedure, whether or not the circuit configuration relating to asynchronous transfer is appropriate as a synchronization circuit for a single-signal transfer.
4. The clock domain check program according to claim 3 ,
wherein the stationary signal is set to a fixed logic value of either “0” or “1” and the logic value does not change when other signals that perform asynchronous crossing change in the asynchronous transfer.
5. A computer-readable recording medium having a clock domain check program according to claim 4 recorded thereon.
6. A computer-readable recording medium having a clock domain check program according to claim 3 recorded thereon.