Element substrate, recording head using the element substrate, and recording apparatus
A buffer circuit for shaping a waveform of a logic signal is arranged where a line for a logic circuit included in a recording-head substrate is divided into substantially equal portions, the line having an unignorable parasitic component due to its increased length. Therefore, the recording-head substrate, a recording head using the recording-head substrate, and a recording apparatus including the recording head are capable of minimizing the adverse effects of parasitic resistance and parasitic capacitance in lines even when the length of a heater array is increased.
1. A recording-head element substrate comprising:
a plurality of blocks, wherein the plurality of blocks include a first block and a second block, each block including a plurality of recording elements, a driving circuit for driving the plurality of recording elements, and a controlling circuit for controlling the driving circuit, the first block including a first shift register, the second block including a second shift register;
a plurality of reception terminals for receiving a driving data signal, a clock signal for controlling capturing the driving data signal by the first and second shift registers and an enable signal specifying a time that the driving circuit drives a recording element;
a set of signal lines for transferring the driving data signal and the clock signal from the reception terminal to the first shift register included in the first block, for transferring the driving data signal and the clock signal from the first shift register included in the first block to the second shift register included in the second block, for transferring the enable signal from the reception terminal to the driving circuit included in the first block, and for transferring the enable signal from the driving circuit included in the first block to the driving circuit included in the second block; and
a plurality of elements for shaping a waveform of the driving data signal, the clock signal and the enable signal in the set of signal lines, the elements being disposed between the first shift register included in the first block and the second shift register included in the second block and being disposed between the driving circuit included in the first block and the driving circuit included in the second block in a path of the signal line.
2. The recording-head element substrate according to claim 1 , wherein each of the driving circuits includes a power transistor.
3. The recording-head element substrate according to claim 1 , wherein the controlling circuit includes a decoder and an AND circuit.
4. The recording-head element substrate according to claim 1 , wherein the first shift register and the second shift register receive a recording data signal based on the control signal.