IP Library Granted Patent US 8,306,494
Granted Patent B2
US 8,306,494 · App. 12/191,637 · Granted Nov 6, 2012

Method and system for a single-ended input low noise amplifier with differential output

Assignee: Broadcom Corporation
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Quick Facts
Patent No.
US 8,306,494
App. No.
12/191,637
Granted
Nov 6, 2012
Kind
B2
Abstract

Methods and systems for a single-ended input low noise amplifier (LNA) with differential output are disclosed and may include configuring the LNA and/or a balun on a chip for single-ended or differential mode, which may function as a load for the LNA. A frequency response and gain of the LNA may be configured via switched capacitors and resistors, which may include CMOS transistors. A transition frequency, and thus impedance matching and matching network gain, may be tuned via configurable gate-source capacitors. A received signal may be filtered via a surface acoustical wave (SAW) filter. The LNA may be impedance matched with an input device via the transition frequency tuning and off chip inductors and/or capacitors. The LNA may be configured for single-ended or differential input mode via switches outside of a signal path to the LNA and reverse isolation may be enabled via a cascode device.

Claims (29)

1. A method for processing signals, the method comprising: in a wireless receiver:

configuring a low noise amplifier (LNA) on a chip for single-ended input mode or differential input mode via switches outside of a signal path to said LNA, wherein said LNA comprises CMOS transistors;

configuring a balun within said chip in said single-ended input mode or said differential input mode, wherein said balun functions as a load for said LNA; and

tuning a transition frequency of said LNA via configurable gate-source capacitors coupled to said CMOS transistors.

2. The method according to claim 1 , comprising configuring a frequency response of said LNA via switched capacitors at an output of said LNA.

3. The method according to claim 1 , comprising configuring a gain of said LNA via switched resistors at an output of said LNA.

4. The method according to claim 1 , comprising configuring a matching network gain via said transition frequency tuning.

5. The method according to claim 1 , comprising impedance matching said LNA with an input device via said transition frequency tuning.

6. The method according to claim 1 , comprising impedance matching said LNA with an input device via off-chip inductors and/or capacitors and one or more on-chip inductors.

7. The method according to claim 1 , comprising filtering a received signal in said wireless receiver via a surface acoustical wave (SAW) filter.

8. The method according to claim 1 , comprising enabling reverse isolation via a cascode device in said LNA.

9. A system for processing signals, the system comprising:

one or more circuits in a wireless receiver, said one or more circuits comprising a low noise amplifier (LNA) and a balun, wherein said one or more circuits comprise CMOS transistors within said LNA, wherein said one or more circuits comprise configurable gate-source capacitors, and wherein said one or more circuits are enabled to:

configure said LNA for single-ended input mode or differential input mode;

configure said balun to operate in said single-ended input mode or said differential input mode, wherein said balun functions as a load for said LNA; and

tune a transition frequency of said LNA via said configurable gate-source capacitors coupled to said CMOS transistors,

wherein said one or more circuits comprise switches outside of a signal path to said LNA, and said one or more circuits are operable to configure said LNA for said single-ended input mode or said differential input mode via said switches outside of said signal path to said LNA.

10. The system according to claim 9 , wherein said one or more circuits comprise switched capacitors, and said one or more circuits are operable to configure a frequency response of said LNA via said switched capacitors that are at an output of said LNA.

11. The system according to claim 9 , wherein said one or more circuits comprise switched resistors, and said one or more circuits are operable to configure a gain of said LNA via said switched resistors that are at an output of said LNA.

12. The system according to claim 9 , wherein said one or more circuits are operable to configure a matching network gain via said transition frequency tuning.

13. The system according to claim 9 , wherein said one or more circuits are operable to impedance match said LNA with an input device via said transition frequency tuning.

14. The system according to claim 9 , wherein said one or more circuits are operable to impedance match said LNA with an input device via off-chip inductors and/or capacitors and one or more on-chip inductors.

15. The system according to claim 9 , wherein said one or more circuits comprise a surface acoustical wave (SAW) filter, and said one or more circuits are operable to filter a received signal in said wireless receiver via said surface acoustical wave (SAW) filter.

16. The system according to claim 9 , wherein said one or more circuits comprise a cascode device, and said one or more circuits are operable to enable reverse isolation via said cascode device in said LNA.

17. A system, comprising:

a low noise amplifier (LNA) on a chip;

switches for configuring said low noise amplifier (LNA) for single-ended input mode or differential input mode, wherein said switches are outside of a signal path to said LNA;

a balun within the chip configured to provide a load for said LNA; and

gate-source capacitors configured to provide a tunable matching network gain and tunable impedance matching of said LNA via a programmable transition frequency of said LNA.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 09/05/2018 PREVIOUSLY RECORDED AT REEL: 047230 FRAME: 0133. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0456 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047230/0133 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2010
From: OJO, ADEDAYO
To: BROADCOM CORPORATION
Reel/Frame 023824/0949 →
Continuity (1)
Related Publication 20100041361A1 · Feb 18, 2010