IP Library Granted Patent US 8,316,171
Granted Patent B2
US 8,316,171 · App. 12/835,623 · Granted Nov 20, 2012

Network on chip (NoC) with QoS features

Assignee: Arteris S.A.
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Quick Facts
Patent No.
US 8,316,171
App. No.
12/835,623
Granted
Nov 20, 2012
Kind
B2
Abstract

Quality-of-Servitrce (QoS) is an important system-level requirement in the design and implementation of on-chip networks. QoS requirements can be implemented in an on-chip-interconnect by providing for at least two signals indicating priority at a transaction-level interface where one signal transfers information in-band with the transaction and the other signal transfers information out-of-band with the transaction. The signals can be processed by the on-chip-interconnect to deliver the required QoS. In addition, the disclosed embodiments can be extended to a Network-on-Chip (NoC).

Claims (45)

1. A method of transmitting priority information at a transaction-level interface of an on-chip-interconnect, comprising:

defining a first signal that transmits priority information in-band with a transaction-level request; and

defining a second signal that transmits priority information out-of-band with regards to transaction-level requests, where the second signal indicates that at least one transaction that originated from the transaction-level interface is to be processed by the on-chip-interconnect with a priority no less than as indicated by a value of the second signal.

2. The method of claim 1 , further comprising:

defining a third signal that transmits priority information out-of-band with regards to transaction-level requests, where the third signal indicates that, on initiator-target paths originating from the transaction-level interface, at least one request of a transaction that is subject to back-pressure is to be processed by the on-chip-interconnect with a priority no less than as indicated by the value of the second signal.

3. The method of claim 2 , where the priority information derived from the value on the third signal is transferred out-of-band on initiator-target paths originating from the initiator interface along paths where requests are subject to back-pressure until a point where a request on a link is not subject to back-pressure.

4. The method of claim 2 , where a value of at least one signal indicating priority on the transaction-level interface is remapped onto a different value by the on-chip-interconnect.

5. The method of claim 2 , where the value of at least one signal indicating priority on the transaction-level interface is encoded using bar-graph encoding.

6. The method of claim 1 , where both the request and response of the transaction are processed by the on-chip-interconnect with a priority no less than as indicated by the value on the second signal.

7. The method of claim 1 , where a decision whether the response of the transaction is processed by the on-chip-interconnect with a priority no less than as indicated by the value of the second signal is determined by an attribute of the transaction-level request.

8. The method of claim 1 , where a decision whether the response of the transaction is processed by the on-chip-interconnect with a priority no less than as indicated by the value of the second signal is configured in the on-chip-interconnect.

9. The method of claim 8 , where the decision whether the response of the transaction is processed with the priority is configured through a Graphical User Interface.

10. The method of claim 1 , where a value of at least one signal indicating priority on the transaction-level interface is remapped onto a different value by the on-chip-interconnect.

11. The method of claim 1 , where the value of at least one signal indicating priority on the transaction-level interface is encoded using bar-graph encoding.

12. The method of claim 1 , where the priority information derived from the value on the first signal is transferred in-band with the transfer associated with the transaction-level transfer as it is processed by the on-chip-interconnect.

13. The method of claim 12 , where the on-chip-interconnect is a Network-On-Chip.

14. The method of claim 13 , where the in-band transfer of priority information is included in a header of the packet.

15. The method of claim 12 , where the priority information that is transferred in-band is transferred to an out-of-band signal along paths where requests are subject to back-pressure, originating from a first arbitration point where a request is subject to back-pressure until a point where a request on a link is not subject to back-pressure.

16. The method of claim 15 , where the on-chip-interconnect is a Network-On-Chip.

17. The method of claim 16 , where in-band transfer is implemented by carrying the in-band information in a header of a packet associated with the transaction request.

18. The method of claim 15 , where the priority information on the second signal is encoded using bar-graph encoding.

19. The method of claim 12 , where the out-of -band priority information is transferred from the on-chip-interconnect logic to a protocol-defined signal that is part of a target transaction level interface.

20. The method of claim 1 , where the on-chip-interconnect is a Network-On-Chip.

21. The method of claim 1 , where in-band transfer is implemented by carrying the in-band information in a header of a packet associated with the transaction request.

22. The method of claim 1 , where an encoding of a signal of the transaction-level interface is different for a second transaction-level interface of the on-chip-interconnect.

23. The method of claim 1 , further comprising:

defining a third signal; and

when a value of the third signal is greater than a value of a most recent previously transmitted request, sending a null request with the value of the second signal assigned to the value of the third signal.

24. The method of claim 23 , where the value of the first signal of a multiplicity of most recent previously transmitted requests are stored in a table in which table entries correspond to routes through the on-chip-interconnect.

25. A method of transmitting priority information at a transaction-level interface of an on-chip-interconnect, comprising:

receiving in-band priority information at the transaction-level interface;

receiving out-of-band priority information at the transaction-level interface; and

processing transaction requests subject to back-pressure, where the processing is performed with a priority based on a first value on the in-band signal and a second value on the out-of-band signal, and where the priority is no less than as indicated by the second value on the out-of-band signal.

26. The method of claim 25 wherein the first value or the second value is determined by a bandwidth requirement of a data-flow.

27. The method of claim 25 wherein the first value or the second value is determined by a bandwidth regulator.

28. The method of claim 25 wherein the in-band priority information is encoded in a packet.

29. The method of claim 25 wherein the processing is performed by a memory scheduler.

30. The method of claim 25 wherein the first value or the second value is determined by a latency requirement of a data-flow.

31. The method of claim 29 wherein the transaction-level interface uses the AXI protocol.

32. The method of claim 29 further comprising receiving out-of-band priority information at a second transaction-level interface where the processing is performed with a priority based on the second value and a third value on the out-of-band signal of the second transaction-level interface, and where the priority is no less than as indicated by the third value.

33. A method of transmitting transactions through an on-chip-interconnect wherein each transaction is assigned a distinct priority level by a source or at a source interface, and wherein the priority of at least one transaction blocked at an arbitration point for access to a destination is propagated ahead of the arbitration point and thereby determines the order in which the transactions are completed.

34. The method of claim 33 , wherein priority is assigned based on a fullness of a write first-in-first-out (FIFO) or emptiness of a read FIFO at a transaction initiator.

35. The method of claim 33 , wherein the on-chip-interconnect contains multiple transactions in FIFOs and an initiator causes the transmission of a new transaction that changes the priority of one or more other transactions within the on-chip-interconnect.

36. The method of claim 33 , wherein a transaction changes the priority of existing transactions within FIFOs along a single route between an initiator interface and a target interface.

37. The method of claim 33 , wherein a transaction is automatically generated in response to a measurement of data transmission bandwidth usage within the interconnect.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 18, 2013
From: ARTERIS, SAS
To: QUALCOMM TECHNOLOGIES, INC.
Reel/Frame 031437/0901 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 28, 2010
From: BOUCARD, PHILIPPE; MARTIN, PHILIPPE; LECLER, JEAN-JACQUES
To: ARTERIS S.A.
Reel/Frame 025544/0926 →
Priority Claims (1)
FR 10 54339 · Jun 3, 2010 · national
Continuity (1)
Related Publication 20110302345A1 · Dec 8, 2011