IP Library Granted Patent US 8,327,047
Granted Patent B2
US 8,327,047 · App. 13/038,266 · Granted Dec 4, 2012

Buffer manager and methods for managing memory

Assignee: Marvell World Trade Ltd.
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,327,047
App. No.
13/038,266
Granted
Dec 4, 2012
Kind
B2
Abstract

Some of the embodiments of the present disclosure provide a method comprising managing a plurality of buffer addresses in a system-on-chip (SOC); and if a number of available buffer addresses in the SOC falls below a low threshold value, obtaining one or more buffer addresses from a memory, which is external to the SOC, to the SOC. Other embodiments are also described and claimed.

Claims (43)

1. A method comprising:

managing a first internal buffer pointer pool and a second internal buffer pointer pool of a system-on-chip (SOC); and

if a number of available buffer addresses in the first internal buffer pointer pool falls below a first low threshold value, obtaining one or more buffer addresses from a first external buffer pointer pool of a memory, which is external to the SOC, to the first internal buffer pointer pool;

if a number of available buffer addresses in the second internal buffer pointer pool falls below a second low threshold value, obtaining another one or more buffer addresses from a second external buffer pointer pool of the memory to the second internal buffer pointer pool;

associating the first internal buffer pointer pool with a first traffic flow such that available buffer addresses from the first internal buffer pointer pool are assigned to data packets of the first traffic flow, wherein the first traffic flow originates from a first client component; and

associating the second internal buffer pointer pool with a second traffic flow such that available buffer addresses from the second internal buffer pointer pool are assigned to data packets of the second traffic flow, wherein the second traffic flow originates from a second client component,

wherein obtaining the one or more buffer addresses from the first external buffer pointer pool to the first internal buffer pointer pool further comprises:

receiving an allocation request for a buffer location from the first client component,

in response to receiving the allocation request, assigning a first buffer address from the first internal buffer pointer pool to the first client component by assigning a first buffer pointer from the first internal buffer pointer pool to the first client component, wherein the first buffer pointer includes the first buffer address,

in response to assigning the first buffer address to the first client component, marking the first buffer address as an unavailable buffer address in the first internal buffer pointer pool,

in response to marking the first buffer address as an unavailable buffer address, if the number of available buffer addresses in the first internal buffer pointer pool falls below the low threshold value, obtaining the one or more buffer addresses from the first external buffer pointer pool to the first internal buffer pointer pool,

wherein the method further comprises buffering, by the first client component, a data packet received by the first client component to a buffer location corresponding to the first buffer address, based at least in part on assigning the first buffer address to the first client component.

2. The method of claim 1 , further comprising:

if the number of available buffer addresses in the first internal buffer pointer pool exceeds a high threshold value, allocating a first one or more buffer addresses from the first internal buffer pointer pool to the first external buffer pointer pool.

3. The method of claim 1 , wherein said managing the first internal buffer pointer pool further comprises:

managing a plurality of buffer pointers in the first internal buffer pointer pool, wherein a buffer pointer of the plurality of buffer pointers includes a corresponding buffer address.

4. A method comprising:

managing a plurality of buffer addresses in a first internal buffer pointer pool of a system-on-chip (SOC);

if a number of available buffer addresses in the first internal buffer pointer pool falls below a low threshold value, obtaining one or more buffer addresses from an external buffer pointer pool of memory, which is external to the SOC, to the first internal buffer pointer pool;

receiving an allocation request for a buffer location from a client component to buffer a data packet received by the client component;

selecting, in response to the allocation request, one of the first internal buffer pointer pool and a second internal buffer pointer pool for allocating a buffer address to the client component, based at least in part on (i) a size of the data packet, (ii) a size of a buffer location associated with the first internal buffer pointer pool, and (iii) a size of a buffer location associated with the second internal buffer pointer pool; and

assigning a buffer address, associated with the selected internal buffer pointer pool, to the client component by assigning a corresponding buffer pointer to the client component.

5. The method of claim 2 , wherein said allocating the first one or more buffer addresses further comprises:

receiving a release request from the first client component, requesting to release a first buffer location associated with a second buffer address;

releasing the first buffer location in response to the release request;

marking the second buffer address as an available buffer address in the first internal buffer pointer pool, in response to releasing the first buffer location; and

in response to marking the second buffer address as an available buffer address in the first internal buffer pointer pool, if the number of available buffer addresses in the first internal buffer pointer pool exceeds the high threshold level, allocating the first one or more buffer addresses from the first internal buffer pointer pool to the first external buffer pointer pool.

6. The method of claim 1 , wherein said one or more buffer addresses comprises a first plurality of buffer addresses, wherein said obtaining the first plurality of buffer addresses from the first external buffer pointer pool to the first internal buffer pointer pool further comprises:

transmitting the first plurality of buffer addresses from the first external buffer pointer pool to the first internal buffer pointer pool as a single transaction between the first external buffer pointer pool and the first internal buffer pointer pool.

7. A system-on-chip (SOC) comprising:

a client component; and

a buffer management unit (BMU) comprising:

a first internal buffer pointer pool (IBPP);

a second IBPP; and

a controller configured to:

monitor (i) a number of unassigned buffer pointers in the first IBPP and (ii) a number of unassigned buffer pointers in the second IBPP,

if the number of unassigned buffer pointers in the first IBPP falls below a first threshold value, allocate a first one or more buffer pointers from a first external buffer pointer pool (EBPP) to the first IBPP, wherein each of the first one or more buffer pointers in the first IBPP points to corresponding buffer locations of a memory that is external to the SOC,

if the number of unassigned buffer pointers in the second IBPP falls below a second threshold value, allocate a second one or more buffer pointers from a second EBPP to the second IBPP, and

if the number of unassigned buffer pointers in the first IBPP exceeds a high threshold value, allocate a third one or more buffer pointers from the first IBPP to the first EBPP.

8. The SOC of claim 7 , wherein the client component is a processing core that is separate from the BMU.

9. The SOC of claim 7 , wherein the client component is a network interface.

10. The SOC of claim 7 , wherein the first EBPP is stored in a memory that is external to the SOC.

11. The method of claim 1 , wherein each of the first client component and the second client component is one of a processing core and a network interface.

Assignments (15)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2020
From: CAVIUM INTERNATIONAL
To: MARVELL ASIA PTE, LTD.
Reel/Frame 053475/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2020
From: MARVELL INTERNATIONAL LTD.
To: CAVIUM INTERNATIONAL
Reel/Frame 052918/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 29, 2020
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 051778/0537 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2012
From: MARVELL ISRAEL (M.I.S.L) LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 029235/0726 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 2, 2012
From: MARVELL INTERNATIONAL LTD.
To: MARVELL WORLD TRADE LTD
Reel/Frame 029235/0800 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2011
From: MARVELL SEMICONDUCTOR, INC.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 026385/0047 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2011
From: MARVELL INTERNATIONAL, LTD.
To: MARVELL WORLD TRADE LTD.
Reel/Frame 026385/0080 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2011
From: PAIS, ALON
To: MARVELL ISRAEL (M.I.S.L) LTD.
Reel/Frame 026384/0953 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2011
From: BISHARA, NAFEA
To: MARVELL SEMICONDUCTOR, INC.
Reel/Frame 026385/0010 →
LICENSE Recorded Jun 3, 2011
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 026385/0027 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2011
From: PAIS, ALON
To: MARVELL ISRAEL (M.I.S.L) LTD.
Reel/Frame 025885/0595 →
LICENSE Recorded Mar 2, 2011
From: MARVELL WORLD TRADE LTD.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 025885/0675 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2011
From: MARVELL SEMICONDUCTOR, INC.
To: MARVELL INTERNATIONAL LTD.
Reel/Frame 025885/0662 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2011
From: BISHARA, NAFEA
To: MARVELL SEMICONDUCTOR, INC.
Reel/Frame 025885/0608 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 2, 2011
From: MARVELL INTERNATIONAL, LTD.
To: MARVELL WORLD TRADE LTD.
Reel/Frame 025885/0665 →
Continuity (3)
Provisional Application 61315327 · Mar 18, 2010
Provisional Application 61347947 · May 25, 2010
Related Publication 20110296063A1 · Dec 1, 2011