Integrated upstream amplifier for cable modem and cable set-top boxes
An upstream amplifier is integrated on a substrate with a digital-to-analog converter (DAC) to form an integrated circuit. In an embodiment, a low-pass filter is also integrated on the substrate. The output signal level of the upstream amplifier is controllable. In embodiments, fine adjustments are made to the output signal level of the upstream amplifier by varying a bias current of the DAC. A software control bit is used to switch between a power-on mode of operation and a power-down mode of operation. The upstream amplifier transmits in a burst mode. The power consumption of the upstream amplifier scales with the amplifier's output signal level. A high degree of matching is attained between the positive and negative paths of the upstream amplifier. This provides high immunity from common-mode disturbances such as substrate noise, clock spurs, and glitches caused by a gain change.
1. An integrated circuit (IC) comprising:
a digital-to-analog converter configured to output a first differential signal; and
an amplifier configured to process the first differential signal, and to output second differential signal, including
a positive input section having a first internal transistor configured to receive a first input signal of the first differential signal;
a negative input section having a second internal transistor configured to receive a second input signal of the first differential signal; and
a plurality of current mirror output transistors configured to output the second differential signal, a first number of the current mirror output transistors being coupled to the first internal transistor to form a first current mirror to produce a first output signal of the second differential signal, and a second number of current mirror output transistors being coupled to the second internal transistor to produce the second output signal of the second differential signal; and
a digital control unit configured to output first control signals to select the first number of the current mirror output transistors that contribute to the first output signal, and to output second control signals to select the second number of current mirror output transistors that contribute to the second output signal.
2. The IC of claim 1 , wherein the first input signal includes a first adjustable bias current provided by a first current source, and the second input signal includes a second adjustable bias current provided by a second current source.
3. The IC of claim 1 , wherein a current gain of the amplifier is varied by adjusting the selection of the first number of current mirror output transistors that contribute to the first output signal, and by adjusting the selection of the second number of current mirror output transistors that contribute to the second output signal.
4. The IC of claim 1 , further comprising:
a plurality of switches having respective inputs coupled to corresponding outputs of the plurality of current mirror output transistors, wherein each switch of the plurality of switches is controlled by a corresponding one of the first or second control signals, so as to determine whether its corresponding current mirror contributes current to one of the first or second output signals.
5. The IC of claim 4 , wherein a current gain of the amplifier is varied by increasing or decreasing the number of switches that are activated to allow current from the corresponding current mirror output transistors to contribute the first or second output signals.
6. The IC if claim 4 , further comprising:
a plurality of cascode transistors, having respective inputs coupled to corresponding outputs of the plurality of switches, each cascade transistor having a common gate voltage that determines one of an on-mode or an off-mode of the amplifier.
7. The IC of claim 6 , further comprising:
an internal transistor amplifier configured to produce the common gate voltage for the plurality of cascade transistors;
a level shifter coupled to the input port of the internal transistor amplifier;
a switch configured to couple the level shifter to a voltage source or to a current sink to ground.
8. The IC of claim 1 , wherein the first input signal includes a first adjustable bias current provided by a first current source, and the second input signal includes a second adjustable bias current provided by a second current source, and wherein the digital control circuit determines the first adjustable bias current provided by a first current source, and the second adjustable bias current provided by a second current source, so as to improve linearity of the amplifier.
9. The IC of claim 1 , wherein at least one current mirror transistor is scaled relative to another current mirror transistor.
10. The IC of claim 1 , wherein the first number of current mirror output transistors are isolated from the second number of current mirror output transistors.
11. The IC of claim 1 , wherein the first input signal is out of phase with respect to the second input signal.
12. The IC of claim 1 , wherein the first number of current mirror output transistors is equal to the second number of current mirror output transistors.
13. The IC of claim 1 , wherein the amplifier comprises:
an electro-static protection circuit configured to protect components included in the amplifier.
14. The IC of claim 1 , wherein one of the first internal transistor or the second internal transistor is diode connected to as to lower the input impedance of the amplifier.
15. The IC of claim 1 , wherein the first number of current mirror output transistors selected to contribute to the first output signal is determined independent from the second number of current mirror output transistors selected to contribute to the second output signal.
16. The IC of claim 1 , wherein at least one of the first control signals or the second control signals operate according to a thermometer code.
17. The IC of claim 1 , wherein at least one current mirror transistor is scaled in a binary fashion relative to another current mirror transistor.