IP Library Granted Patent US 8,357,607
Granted Patent B2
US 8,357,607 · App. 12/936,960 · Granted Jan 22, 2013

Method for fabricating nitride-based semiconductor device having electrode on

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Quick Facts
Patent No.
US 8,357,607
App. No.
12/936,960
Granted
Jan 22, 2013
Kind
B2
Abstract

A nitride-based semiconductor light-emitting device 100 includes a GaN substrate 10 , of which the principal surface is an m-plane 12 , a semiconductor multilayer structure 20 that has been formed on the m-plane 12 of the GaN-based substrate 10 , and an electrode 30 arranged on the semiconductor multilayer structure 20 . The electrode 30 includes an Mg alloy layer 32 which is formed of Mg and a metal selected from a group consisting of Pt, Mo, and Pd. The Mg alloy layer 32 is in contact with a surface of a p-type semiconductor region of the semiconductor multilayer structure 20.

Claims (19)

1. A method for fabricating a nitride-based semiconductor device, comprising the steps of:

(a) providing a substrate;

(b) forming on the substrate a nitride-based semiconductor multilayer structure including a p-type GaN-based semiconductor region, a surface of the p-type GaN-based semiconductor region being an m-plane; and

(c) forming an electrode on the surface of the p-type GaN-based semiconductor region of the semiconductor multilayer structure,

wherein step (c) includes forming an Mg alloy layer on the surface of the p-type Gan-based semiconductor region, the Mg alloy layer being made of Mg and a metal selected from a group consisting of Pt, Mo, and Pd,

wherein a heat treatment is performed to anneal the electrode at a temperature of 500°C. to 700°C., and

wherein a contact resistance of the electrode arranged on the m-plane and annealed at a temperature of 500°C. to 700°C. is less than 1.0×10 −02 Ω cm 2 , and is lower than a contact resistance when the electrode is arranged on a c-plane of the same p-type semiconductor region and annealed at a temperature of 500°C. to 700°C.

2. The method of claim 1 , wherein the heat treatment is performed at a temperature of 550° C. to 650° C.

3. The method of claim 1 , wherein the p-type GaN-based semiconductor region is made of an Al x In y Ga z N semiconductor (where x+y+z=1, x≧0, y≧0, and z>0).

4. The method of claim 3 , wherein the step of forming the Mg alloy layer includes

forming an Mg layer on the surface of the p-type GaN-based semiconductor region,

forming on the Mg layer a conductive layer selected from a group consisting of Pt, Mo, and Pd, and

performing the heat treatment to alloy the Mg layer and at least part of the conductive layer.

5. The method of claim 4 , wherein the step of forming the Mg layer includes irradiating Mg with pulses of an electron beam such that Mg is deposited onto the surface of the p-type GaN-based semiconductor region.

6. The method of claim 4 , wherein the Mg layer is deposited on the semiconductor multilayer structure so as to have a thickness of 0.1 nm to 5 nm.

7. The method of claim 3 , further comprising removing the substrate after step (b).

8. The method of claim 3 , wherein the step of forming the Mg alloy layer includes

depositing a mixture or compound of Mg and a metal selected from a group consisting of Pt, Mo, and Pd onto the surface of the p-type GaN-based semiconductor region by means of evaporation, and

performing a heat treatment.

Assignments (2)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →