Active matrix electrochromic device array and method of manufacturing the same

1. An active matrix electrochromic device array comprising:

a first substrate including a pixel circuit having a plurality of pixel electrodes, wherein the plurality of pixel electrodes are two-dimensionally arrayed, a thin film transistor (TFT) connected to each of the plurality of pixel electrodes, and a plurality of electrochromic layers on the plurality of pixel electrodes, respectively;

a second substrate including a counter electrode and a reflective layer thereon, wherein the second substrate is coupled to the first substrate having a distance therebetween and the reflective layer faces the plurality of electrochromic layers;

a partition wall between the first substrate and the second substrate so as to support the first substrate and the second substrate having a distance therebetween, the first and second substrate having isolating spaces therebetween corresponding to the plurality of pixel electrodes; and

an electrolyte filled in the spaces isolated by the first substrate, the second substrate, and the partition wall.

2. The active matrix electrochromic device array of claim 1 , wherein the partition wall further comprises a supporting partition wall arranged in an upper region of the TFT.

3. The active matrix electrochromic device array of claim 1 , wherein the partition wall is formed of a photoresist.

4. The active matrix electrochromic device array of claim 3 , wherein the partition wall is a black matrix with respect to pixels.

5. The active matrix electrochromic device array of claim 3 , wherein the partition wall is non-porous.

6. The active matrix electrochromic device array of claim 1 , wherein the partition wall is formed to have a height of about 50 μm.

7. The active matrix electrochromic device array of claim 1 , wherein the partition wall is a black matrix defining pixels.

8. The active matrix electrochromic device array of claim 1 , wherein the partition wall is non-porous.

9. The active matrix electrochromic device array of claim 1 , wherein the partition wall is formed by extending toward an outer region of an area including the plurality of pixel electrodes.

10. A method of manufacturing an active matrix electrochromic device array, the method comprising:

providing a first substrate including a pixel circuit having a plurality of pixel electrodes that are two-dimensionally arrayed and a thin film transistor (TFT) connected to each of the plurality of pixel electrodes;

forming a partition wall in the first substrate, wherein the partition wall isolates a space corresponding to the plurality of pixel electrodes;

forming an electrochromic layer in a region of the first substrate, wherein the partition wall is not formed in the region;

arranging a second substrate over the first substrate, the second substrate including a counter electrode and a reflective layer on the counter electrode;

aligning the first substrate and the second substrate so that the reflective layer faces the electrochromic layer;

injecting an electrolyte into the space isolated by the first substrate, the second substrate, and the partition wall; and

coupling the first substrate and the second substrate.

11. The method of claim 10 , wherein forming the partition wall comprises:

coating a photoresist on the first substrate;

removing the photoresist coated on regions corresponding to the plurality of pixel electrodes; and

hardening the photoresist remaining on the first substrate.

12. The method of claim 11 , wherein coating the photoresist further comprises removing bubbles of the photoresist before the first substrate is coated.

13. The method of claim 11 , wherein a region where the partition wall is formed includes an upper region of the TFT.

14. The method of claim 11 , wherein the partition wall is formed to have a height of at least 50 μm.

15. The method of claim 10 , wherein the partition wall is formed by extending toward an outer region of an area where the plurality of pixel electrodes are arranged.

16. The method of claim 10 , wherein a region where the partition wall is formed includes an upper region of the TFT.

17. The method of claim 10 , wherein forming the electrochromic layer comprises:

forming an electrochromic semiconductor layer in a region where the partition wall of the first substrate is not formed; and

adding an electrochromic material to adsorb onto the electrochromic semiconductor layer.

18. The method of claim 17 , wherein forming the electrochromic semiconductor layer comprises:

coating an electrochromic semiconductor on the region where the partition wall of the first substrate is not formed; and

baking the coated electrochromic semiconductor,

wherein a temperature for baking the coated electrochromic semiconductor is within a temperature range of about 200° C. to about 400° C.