Authentication of integrated circuits
A group of devices are fabricated based on a common design, each device having a corresponding plurality of measurable characteristics that is unique in the group to that device, each device having a measurement module for measuring the measurable characteristics. Authentication of one of the group of devices is enabled by selective measurement of one or more of the plurality of measurable characteristics of the device.
1. An integrated circuit device comprising circuitry for repeated generation of a cryptographic key that depends on fabrication characteristics of the integrated circuit and a multiple bit challenge value, said circuitry comprising:
oscillation circuitry comprising a plurality of oscillators for providing a plurality of oscillatory signals, oscillation frequencies of the oscillatory signals being dependent on fabrication characteristics of the oscillation circuitry and on the multiple bit challenge value;
combination circuitry for processing the oscillatory signals and producing outputs each dependent on multiple of the plurality of oscillatory signals; and
a key generator for assembling the cryptographic key to depend on the outputs of the combination circuitry.
2. The device of claim 1 further comprising:
an error mitigation component for processing the outputs of the combination circuitry prior to assembling the cryptographic key.
3. The device of claim 2 wherein the error mitigation component comprises an error correction component.
4. The device of claim 1 wherein the combination circuitry comprises arithmetic combination circuitry for arithmetically combining quantities representing oscillation frequencies of the multiple oscillatory signals.
5. The device of claim 4 wherein the circuitry for arithmetically combining the quantities comprises circuitry for dividing the quantities.
6. The device of claim 1 wherein each oscillator of the plurality of oscillators comprises a plurality comprises a delay loop whose delay depends on fabrication characteristics of the circuitry.
7. The device of claim 6 wherein the delay loop comprises a series of logic gates.
8. The device of claim 6 wherein the delay of the delay loop is further dependent on the challenge value.
9. The device of claim 1 wherein the oscillation circuitry is configured to provide each oscillatory signal using a different one of the plurality of oscillators.
10. A method for repeated generation of a cryptographic key that depends on fabrication characteristics of an integrated circuit comprising:
operating a plurality of oscillators to provide a plurality of oscillatory signals, oscillation frequencies of the oscillatory signals being dependent on fabrication characteristics of the oscillation circuitry and on a multiple bit challenge value;
combining quantities representing oscillation frequencies of the oscillatory signals to produce outputs each dependent on multiple of the plurality of oscillatory signals; and
assembling a cryptographic key to depend on the outputs of the combining.
11. The method of claim 10 further comprising mitigating errors in the outputs of the combination circuitry prior to assembling the cryptographic key.
12. The method of claim 10 wherein combining the quantities includes arithmetically combining the quantities.
13. The method of claim 12 wherein arithmetically combining the quantities comprises dividing the quantities.
14. The method of claim 10 further comprising repeating generation of the cyptographic key using the multiple bit challenge value previously used to generate the cryptographic key.
15. The device of claim 1 wherein the plurality of oscillators is configurable according to the multiple bit challenge value.