Method for introducing channel stress and field effect transistor fabricated by the same
The present invention relates to CMOS ultra large scale integrated circuits, and provides a method for introducing channel stress and a field effect transistor fabricated by the same. According to the present invention, a strained dielectric layer is interposed between source/drain regions and a substrate of a field effect transistor, and a strain is induced in a channel by the strained dielectric layer which directly contacts the substrate, so as to improve a carrier mobility of the channel and a performance of the device. The specific effects of the invention include: a tensile strain may be induced in the channel by using the strained dielectric layer having a tensile strain in order to increase an electron mobility of the channel; a compressive strain may be induced in the channel by using the strained dielectric layer having a compressive strain in order to increase a hole mobility of the channel. According to the invention, not only an effectiveness of the introduction of channel stress is ensued, but the device structure of the field effect transistor is also improved fundamentally, so that a capability for suppressing a short channel effect of the device is increased.
1. A method for fabricating a field effect transistor, comprising the following steps:
1) etching source/drain region grooves by using a silicon oxide sacrificial gate as a mask;
2) depositing a strained dielectric layer that directly contacts the source/drain region grooves, and selectively etching the strained dielectric layer by using polysilicon sacrificial source/drain as a protection layer;
3) performing epitaxial growth by using exposed channel windows as seed crystal layers to obtain source/drain regions;
4) performing a light doped LDD implantation, depositing a silicon nitride layer, and performing a source/drain implantation by using the silicon nitride layer as a protection layer;
5) depositing a thick silicon nitride layer, and performing a chemical mechanical polish until the silicon oxide sacrificial gate; and
6) etching and removing the silicon oxide sacrificial gate, obtaining a gate dielectric layer, and depositing a polysilicon layer and performing a chemical mechanical polish to obtain a polysilicon gate.
2. The method according claim 1 , wherein the strained dielectric layer comprising silicon nitride having a tensile stress is obtained by depositing silicon nitride through a low rate plasma enhanced chemical vapor deposition (PECVD) with a film deposition rate smaller than 250 Å/min.
3. The method according to claim 1 , wherein the strained dielectric layer comprising silicon nitride having a compressive stress is obtained by depositing silicon nitride through a plasma enhanced chemical vapor deposition (PECVD) with diluting gas being added into reactive gas.
4. The method according to claim 1 , wherein the strained dielectric layer comprising diamond-like carbon having a compressive stress is obtained by a physical vapor deposition (PVD) or chemical vapor deposition (CVD) method.