IP Library Granted Patent US 8,450,183
Granted Patent B2
US 8,450,183 · App. 12/961,905 · Granted May 28, 2013

Power semiconductor device and method of manufacturing the same

Inventors: Ryoichi Fujii (Tokyo, JP); Shigeto Honda (Tokyo, JP); Atsushi Narazaki (Tokyo, JP); Kaoru Motonami (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
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Quick Facts
Patent No.
US 8,450,183
App. No.
12/961,905
Granted
May 28, 2013
Kind
B2
Abstract

A method of manufacturing a power semiconductor device according to the present invention includes the steps of: (a) forming a silicon nitride film on a semiconductor substrate; (b) after the step (a), forming a ring-shaped trench along a peripheral portion of the semiconductor substrate 6 ; (c) forming a first silicon oxide film on an inner surface of the trench; (d) after the step (c), forming a second silicon oxide film on an entire surface of the semiconductor substrate to bury the trench; (e) planarizing the second silicon oxide film by using the silicon nitride film as a stopper; and (f) forming a third silicon oxide film in a region in which the silicon nitride film is removed.

Claims (20)

1. A method of manufacturing a power semiconductor device, comprising the steps of:

(a) forming a silicon nitride film on a semiconductor substrate;

(b) after said step (a), forming a ring-shaped trench along a peripheral portion of said semiconductor substrate as a terminal structure of a cell region, and defining the inside of the ring as said cell region;

(c) forming a first silicon oxide film on an inner surface of said trench;

(d) after said step (c), forming a second silicon oxide film on an entire surface of said semiconductor substrate to bury said trench;

(e) planarizing said second silicon oxide film by using said silicon nitride film as a stopper; and

(f) removing said silicon nitride film, and then forming a third silicon oxide film in a region in which said silicon nitride film is removed,

wherein said third silicon oxide film is formed by thermal oxidation.

2. The method of manufacturing a power semiconductor device according to claim 1 , wherein

said step (a) is a step of forming said silicon nitride film on an Si substrate or an SiC substrate which serves as said semiconductor substrate.

3. The method of manufacturing a power semiconductor device according to claim 1 , wherein

said step (b) is a step of forming, as said trench, a trench region in which a surface of said semiconductor substrate is scattered in the shape of islands.

4. A power semiconductor device comprising:

a semiconductor substrate in which a ring-shaped trench is formed along a peripheral portion of said semiconductor substrate as a terminal structure of a cell region, the inside of the ring being defined as said cell region;

a first silicon oxide film formed on an inner surface of said trench;

a second silicon oxide film formed on said first silicon oxide film and buried in said trench in such a manner that said first silicon oxide film and said second silicon oxide film completely fill said trench; and

a third silicon oxide film formed on a surface of said semiconductor substrate except said trench,

wherein said trench is formed as a trench part in which the surface of said semiconductor substrate is scattered in the shape of islands.

5. The power semiconductor device according to claim 4 , wherein

said semiconductor substrate is an Si substrate or an SiC substrate.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 7, 2010
From: FUJII, RYOICHI; HONDA, SHIGETO; NARAZAKI, ATSUSHI; MOTONAMI, KAORU
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 025463/0548 →
Priority Claims (1)
JP 2010-052606 · Mar 10, 2010 · national
Continuity (1)
Related Publication 20110220914A1 · Sep 15, 2011