Power amplifying circuit, and transmitter and wireless communication device using the same

1. A power amplifier circuit, comprising:

a constant envelope signal generation circuit for converting an input signal having envelope variation into a first constant envelope signal and a second constant envelope signal which have the same amplitude and different phases so as to output the first constant envelope signal and the second constant envelope signal;

a first amplifier for amplifying the first constant envelope signal, which is input from the constant envelope signal generation circuit, so as to output a first amplified signal;

a second amplifier for amplifying the second constant envelope signal, which is input from the constant envelope signal generation circuit, so as to output a second amplified signal; and

an output adder for outputting an amplified output signal having envelope variation based on the first amplified signal, which is input from the first amplifier, and the second amplified signal, which is input from the second amplifier,

wherein the constant envelope signal generation circuit includes an amplitude control circuit for controlling the amplitude of the first constant envelope signal and the second constant envelope signal based on an amplitude of the input signal wherein the constant envelope signal generation circuit includes:

a fundamental signal generation circuit for generating a first fundamental signal and a second fundamental signal having the same amplitude and predetermined phase relationships with the input signal, and a fundamental signal for conversion having constant phase relationships with the first fundamental signal and the second fundamental signal, from the input signal having envelope variation;

a converted signal generation circuit for generating a first converted signal which has an amplitude Y satisfying Y 2 =A 2 −X 2 , where X denotes the amplitude of the first fundamental signal and the second fundamental signal, and A denotes any constant amplitude larger than X, and which is advanced in phase with respect to the first fundamental signal by π/2, and a second converted signal which has the amplitude Y and is delayed in phase with respect to the second fundamental signal by π/2, by amplifying the fundamental signal for conversion based on the amplitude X of the first fundamental signal and/or the second fundamental signal;

a first adder for performing vector addition of the first fundamental signal and the first converted signal; and

a second adder for performing vector addition of the second fundamental signal and the second converted signal,

wherein the first constant envelope signal is output based on a signal output from the first adder, and the second constant envelope signal is output based on a signal output from the second adder, and

wherein the amplitude control circuit controls a gain of generating the first converted signal and the second converted signal, so as to control the amplitude of the first constant envelope signal and the second constant envelope signal,

wherein the converted signal generation circuit includes:

an amplitude detection signal generation circuit for generating an amplitude detection signal having a DC voltage α corresponding to an amplitude of a signal obtained by vector addition of the first fundamental signal and the first converted signal, and a signal obtained by vector addition of the second fundamental signal and the second converted signal;

a subtractor for outputting, in a case where a reference signal having any DC voltage β larger than the DC voltage α and the amplitude detection signal are input, a signal having a DC voltage γ satisfying γ=β−α; and

a variable gain amplifier for amplifying the fundamental signal for conversion, based on a gain control signal based on the signal output from the subtractor, so that the amplitude Y of the first converted signal and the second converted signal satisfies Y 2 =A 2 −X 2 , and

wherein the amplitude control circuit controls the DC voltage β of the reference signal based on the amplitude of the input signal so as to control the amplitude of the first constant envelope signal and the second constant envelope signal.

2. The power amplifier circuit according to claim 1 , wherein the amplitude control circuit controls the amplitude of the first constant envelope signal and the second constant envelope signal so that the amplitude of the first constant envelope signal and the second constant envelope signal decreases step by step as the amplitude of the input signal decreases.

3. A transmitter comprising a transmission circuit and an antenna which are connected via the power amplifier circuit according to claim 2 .

4. A wireless communication device comprising a transmission circuit and an antenna which are connected via the power amplifier circuit according to claim 2 and a reception circuit connected to the antenna.

5. The power amplifier circuit according to claim 1 , further comprising a circuit for controlling the first amplifier and the second amplifier, in synchronization with a variation of the amplitude of the first constant envelope signal and the second constant envelope signal, so that an operating point of amplifying the first constant envelope signal and the second constant envelope signal is in a saturation region.

6. A transmitter comprising a transmission circuit and an antenna which are connected via the power amplifier circuit according to claim 5 .

7. A wireless communication device comprising a transmission circuit and an antenna which are connected via the power amplifier circuit according to claim 5 and a reception circuit connected to the antenna.

8. A transmitter comprising a transmission circuit and an antenna which are connected via the power amplifier circuit according to claim 1 .

9. A wireless communication device comprising a transmission circuit and an antenna which are connected via the power amplifier circuit according to claim 1 , and a reception circuit connected to the antenna.