Phase-locked loop

1. A phase-locked loop (PLL), comprising:

an active filter, comprising a first input, a second input, and an output for providing a control signal;

a voltage-controlled oscillator (VCO) that generates an oscillation signal according to the control signal;

a first phase detector that generates a phase difference signal according to a reference signal and a feedback signal, the feedback signal associated with the oscillation signal;

a charge pump that provides a charging current to the first input of the active filter according to the phase difference signal;

a second phase detector that generates a digital reference signal according to a phase difference between the reference signal and the feedback signal, the second phase detector generating the digital reference signal with differently valued multi-segment digital unit values as input; and

a digital-to-analog converter (DAC) that converts the digital reference signal to an analog reference signal which is fed to the active filter.

2. The PLL according to claim 1 , further comprising:

a capacitor, coupled to the second input of the active filter;

a switch, coupled between the second input and the DAC; and

a switch module that controls the switch to disconnect a link between the DAC and the second input.

3. The PLL according to claim 1 , wherein the digital reference signal is fixed at a predetermined voltage when the phase difference is greater than a threshold.

4. The PLL according to claim 1 , wherein the active filter comprises an operational amplifier, a capacitor, and a resistor, wherein two inputs of the operational amplifier are respectively the first input and the second input, and wherein the capacitor and the resistor are connected in parallel between the first input and the output.

5. The PLL according to claim 1 , wherein the second phase detector comprises an accumulator that generates the digital reference signal, and wherein a positive/negative signal of the phase difference corresponds to a positive/negative signal of an input signal of the accumulator.

6. The PLL according to claim 5 , wherein a change in a speed of the digital reference signal corresponds to a magnitude of the input signal of the accumulator.

7. The PLL according to claim 1 , further comprising:

a frequency divider, coupled to the VCO, that frequency-divides the oscillation signal to generate the feedback signal.

8. A method for controlling a phase-locked loop (PLL), comprising:

providing a control signal by an active filter;

generating an oscillation signal according to the control signal;

generating a phase difference signal according to a reference signal and a feedback signal, the feedback signal associated with the oscillation signal;

providing a charging current to a first input of the active filter according to the phase difference signal;

generating a digital reference signal with differently valued multi-segment digital unit values as input according to a phase difference between the reference signal and the feedback signal; and

converting the digital reference signal to an analog reference signal which is fed to the active filter.

9. The method according to claim 8 , wherein the digital reference signal is fixed at a predetermined voltage when the phase difference is greater than a threshold.

10. The method according to claim 8 , wherein the digital reference signal is generated by an accumulator, and wherein a positive/negative signal of the phase difference corresponds to a positive/negative signal of an input signal of the accumulator.

11. The method according to claim 10 , wherein a change in a speed of the digital reference signal corresponds to a magnitude of the input signal of the accumulator.