Semiconductor device for short-circuiting output terminals of two or more voltage generator circuits at read time and control method for the same

1. A semiconductor device comprising:

a first voltage generator circuit which outputs a first voltage to a first node;

a second voltage generator circuit which outputs a second voltage to a second node;

a first MOS transistor capable of short-circuiting the first node and second node; and

a controller which performs a control operation to short-circuit the first node and second node by turning on the first MOS transistor, controlling a period in which the first MOS transistor is kept in an on state based on time.

2. The device according to claim 1 , wherein a first load is connected to the first node, and a second load larger than the first load is connected to the second node,

when a potential of the first load reaches the second voltage in a case where the first voltage is higher than the second voltage at a read time, the controller turns off the first MOS transistor.

3. The device according to claim 1 , wherein a first load is connected to the first node, and a second load larger than the first load is connected to the second node,

in a case where the second voltage is higher than the first voltage at a read time, the controller turns off the first MOS transistor before a potential of the second load reaches the first voltage.

4. The device according to claim 1 , wherein the first MOS transistor is one of an n-type intrinsic MOS transistor, depression-type MOS transistor, and enhancement-type MOS transistor.

5. The device according to claim 1 , wherein the controller

senses a potential of the second node, and

transfers a voltage equal to the sum of the above potential and a threshold voltage of the first MOS transistor to the gate of the first MOS transistor.

6. The device according to claim 1 , further comprising:

a third voltage generator circuit which outputs a third voltage to a third node; and

a second MOS transistor capable of short-circuiting the second node and the third node,

wherein the controller simultaneously performs on and off switching operations of the first MOS transistor and second MOS transistor.

7. The device according to claim 6 , wherein the controller

senses a potential of one of the second node and the third node, and

transfers one of a first voltage equal to the sum of the above potential and a first threshold voltage of the first MOS transistor and a second voltage equal to the sum of the above potential and a second threshold voltage of the second MOS transistor to the gates of the first and second MOS transistors.

8. The device according to claim 1 , further comprising:

a memory cell array including plural memory cells whose current paths are serially connected and each of which includes a charge storage layer and control gate; and

word lines connected to the control gates of the memory cells and each used as one of the first and second loads;

wherein the first and second voltage generator circuits transfer one of the first and second voltages to the word lines.

9. A semiconductor device comprising:

a memory cell array including i memory cells (i is an integral number larger than 2) capable of holding data each of which includes a charge storage layer and control gate and the i memory cells are serially connected along a current path; and

a voltage generator circuit which generates a first voltage and second voltage, transferring the first and second voltages to word lines connected to the control gates of the memory cells,

wherein the voltage generator circuit

transfers the first voltage to the word line connected to the control gate of the ith memory cell, and

transfers the second voltage to the word lines connected to the control gates of the (i+1)th and (i+2)th memory cells which are arranged on a drain side of the ith memory cell.

10. The device according to claim 9 , wherein the first voltage is a voltage corresponding to data held by the ith memory cell.

11. The device according to claim 9 , further comprising:

a MOS transistor capable of short-circuiting a first node and second node; and

a controller which performs a control operation to turn on the MOS transistor to short-circuit the first node and second node,

wherein the voltage generator circuit includes

a first voltage generator circuit which generates the first voltage and outputs the first voltage to the first node, and

a second voltage generator circuit which generates the second voltage and outputs the second voltage to the second node, and

the controller controls a period in which the MOS transistor is maintained in an on state based on time.

12. The device according to claim 11 , wherein the controller

senses a potential of the second node, and

transfers a voltage equal to the sum of the above

potential and a threshold voltage of the MOS transistor to the gate of the MOS transistor.

13. The device according to claim 9 , wherein the MOS transistor is one of an n-type intrinsic MOS transistor, depression-type MOS transistor, and enhancement-type MOS transistor.

14. The device according to claim 11 , wherein a word line used as a first load is connected to the first node, and a word line used as a second load larger than the first load is connected to the second node, and

in a case where the second voltage is higher than the first voltage, the controller turns off the first MOS transistor before a potential of the second load reaches the first voltage.

15. A control method of a semiconductor device comprising:

causing a first voltage generator circuit to generate a first voltage and output the first voltage to a first node;

causing a second voltage generator circuit to generate a second voltage and output the second voltage to a second node;

causing a controller to set a first MOS transistor in an on state and short-circuit the first node and second node; and

causing the controller to control a period in which the first MOS transistor is maintained in the on state based on time.

16. The method according to claim 15 , further comprising:

causing the first voltage generator circuit to transfer the first voltage to a first load via the first node;

causing the second voltage generator circuit to transfer the second voltage higher than the first voltage to a second load larger than the first load via the second node; and

causing the controller to turn off the first MOS transistor before a potential of the second load reaches the first voltage.

17. The method according to claim 15 , further comprising:

causing the first voltage generator circuit to transfer the first voltage to a first load via the first node;

causing the second voltage generator circuit to transfer the second voltage to a second load larger than the first load via the second node; and

if the first voltage is higher than the second voltage at a read time, causing the controller to turn off the first MOS transistor at the timing of a potential of the first load reaching the second voltage.

18. The method according to claim 15 , further comprising:

causing the controller to sense a potential of the second node; and

causing the controller to transfer a voltage equal to the sum of the above potential and a threshold voltage of the first MOS transistor to the gate of the first MOS transistor.

19. The method according to claim 15 , further comprising:

causing a third voltage generator circuit to generate a third voltage and output the third voltage to a third node;

causing the controller to turn on the first and second MOS transistors and short-circuit the first to third nodes; and

causing the controller to simultaneously perform on and off switching operations of the first and second MOS transistors.

20. The method according to claim 16 , further comprising:

transferring the first voltage to a control gate of an ith memory cell among plural memory cells whose current paths are serially connected via the first node at a data read time; and

transferring the second voltage to a control gate of an (i+1)th memory cell arranged on a drain side of the ith memory cell via the second node.