Generating a random number in an existing system on chip

1. A system comprising:

one or more sub circuitry synchronous modules, each of the one or more sub circuitry synchronous modules being configured to operate in a respective nominal clock rate, wherein each of the one or more sub circuitry synchronous modules yields expected deterministic results when operating in its respective nominal clock rate; and

a control module configured to clock the one or more sub circuitry synchronous modules each in a clock rate higher than its respective nominal clock rate and beyond a specified value, to yield a non deterministic behavior of the one or more sub circuitry synchronous modules, resulting in one or more random signals, wherein the system is implemented within an existing system on chip (SOC).

2. The system according to claim 1 , wherein at least one of the one or more sub circuitry synchronous modules is associated with a process invariance, wherein the non deterministic behavior is due to the process invariance.

3. The system according to claim 1 , further comprising an analog to digital converter configured to convert the one or more random signals into a set of random numbers.

4. The system according to claim 3 , further comprising a hash function module configured to apply a hash function to the set of random numbers to yield a single random number that has a level of randomness beyond a specified level.

5. The system according to claim 1 , further comprising at least one processor and two or more phase lock loops (PLL) modules, wherein at least one of the PLL modules is configured to clock the at least one processor at a respective nominal clock rate, and wherein at least one of the PLL modules are configured to clock the one or more sub circuitry synchronous modules at the higher clock rate beyond the specified value.

6. The system according to claim 1 , wherein the one or more sub circuitry synchronous modules are memory cells.

7. The system according to claim 1 , wherein the one or more sub circuitry synchronous modules are SRAM cells.

8. A method of generating a true random number utilizing a system on chip (SOC), the method comprising:

providing a SOC having a plurality of sub circuitry synchronous modules, each of the plurality of sub circuitry synchronous modules being configured to operate in a respective nominal clock rate, wherein each of, the plurality of sub circuitry synchronous modules exhibit process invariance and yield expected deterministic results while operating in the nominal clock rate;

clocking one or more sub circuitry synchronous modules in a clock rate substantially higher than its respective nominal clock rate to yield a non deterministic behavior of the at least one sub circuitry synchronous module, due to process variance, resulting in at least one random number; and

applying a hash function on the at least one random number thereby generating a number exhibiting a high level of randomness.

9. The method according to claim 8 , further comprising;

providing at least one processor and two or more phase lock loops (PLL) modules;

clocking the at least one processor at a respective nominal clock rate; and

clocking the one or more sub circuitry synchronous modules at the higher clock rate beyond a specified threshold, wherein the clocking is carried out by the PLL modules respectively.

10. The method according to claim 8 , wherein the one or more sub circuitry synchronous modules are memory cells.

11. The method according to claim 8 , wherein the one or more sub circuitry synchronous modules are SRAM cells.