IP Library Granted Patent US 8,532,229
Granted Patent B2
US 8,532,229 · App. 12/461,748 · Granted Sep 10, 2013

Hard iterative decoder for multilevel codes

Inventors: Eric Morgan Dowling (Escazu, CR); John P. Fonseka (Plano, TX)
Assignee: Trellis Phase Communications, LP
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Quick Facts
Patent No.
US 8,532,229
App. No.
12/461,748
Granted
Sep 10, 2013
Kind
B2
Abstract

Two decoding algorithms are introduced for the decoding of multi-level coded modulation and other types of coded modulation involving component codes and interleaving operations. An improved hard iterative decoding (IHID) algorithm is presented that improves upon a hard iteration decoding technique by adding a stopping criterion. Also, a list Viterbi hard iteration decoding (LV-IHID) algorithm is presented that employs list decoding in conjunction with the IHID algorithm. Both of these decoding algorithms improve upon conventional multi-stage decoding by reducing the effective error multiplicity that is observed at the lowest coding level. It is demonstrated that the LV-IHID algorithm performs close to soft iterative decoding. The computational and delay complexity of the proposed decoding algorithms compare favorably with soft iterative decoding strategies. Also, a novel labeling strategy for MLC design is presented.

Claims (12)

1. A method of decoding a coded signal that is encoded in accordance with at least two component codes, to include a first component code (CC 1 ) and a second component code (CC 2 ), comprising:

receiving a communication signal representative of the coded signal, and decoding the communication signal to determine an initial CC 1 decoded sequence and a corresponding initially inherently assumed CC 2 decoded sequence that is inherently assumed in accordance with a sequence of minimum CC 1 branch metrics that identify corresponding elements of the initially inherently assumed CC 2 decoded sequence;

performing an iteration thread starting with the initial CC 1 decoded sequence and the initially inherently assumed CC 2 decoded sequence and stopping the iteration thread when: (i) an inherently-assumed CC 2 decoded sequence is substantially equal to a first-computed CC 2 decoded sequence, (ii) a previously-computed CC 1 decoded sequence is substantially equal to a next-computed CC 1 decoded sequence, and (iii) when a previously-computed CC 2 decoded sequence is substantially equal to a next-computed CC 2 decoded sequence;

making available a decoder output sequence that includes at least a CC 1 decoded sequence and a CC 2 decoded sequence that are substantially equal to a most-recently-computed CC 1 decoded sequence and a most-recently-computed CC 2 decoded sequence as computed just prior to the stopping condition being met.

2. The method of claim 1 , wherein the coded signal is a multilevel coded signal, the CC 1 is a lower level code, and CC 2 is an upper level code.

3. The method of claim 2 , wherein the lower level code is a building-block code (BC), and the upper level code is a tiling code (TC).

4. The method of claim 3 , wherein the decoder output sequence is a multilevel decoded sequence that includes a BC decoded sequence and a TC decoded sequence.

5. The method of claim 4 , wherein the BC and the TC involve convolutional codes, and the BC decoded sequence and the TC decoded sequence are decoded via respective BC and TC Viterbi decoders.

6. The method of claim 5 , wherein the TC Viterbi decoder comprises an in-phase TC Viterbi decoder and a quadrature-phase TC Viterbi decoder.

7. The method of claim 5 , wherein the iteration thread corresponds to a series of iterative multistage decoding (MSD) runs, each MSD run uses a previously decoded BC sequence to assist in computing branch metrics for use in current TC decoder run, and at least one of the MSD runs uses a previously decoded TC sequence to assist in computing branch metrics for use in current BC decoder run.

8. The method of claim 7 , wherein the iteration thread corresponds to a run of an improved hard iterative decoder (IHID) algorithm.

9. The method of claim 1 , wherein the coded signal is a turbo coded signal.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2013
From: DOWLING, ERIC M.; FONSEKA, JOHN P.
To: TRELLIS PHASE COMMUNICATIONS, LP
Reel/Frame 030763/0408 →
Continuity (1)
Related Publication 20110044398A1 · Feb 24, 2011