Off-set top pixel electrode configuration
A semiconductor device architecture where the top pixel electrode is deposited in an off-set configuration, such as to overlap the COM electrode, and also the gate electrode of the neighboring device.
1. A multilayer electronic structure comprising: a substrate bearing at least three conducting layers, adjacent ones of said conducting layers being separated by a dielectric layer, a first one of said conducting layers defining drain and source electrodes of a thin film transistor (TFT) for driving a pixel of an active matrix optoelectronics device, an intermediate second one of said conducting layers defining a gate electrode of said transistor and a first plate of a capacitor for storing charge to maintain an electrical state of said active matrix pixel, and a third one of said conducting layers defining a pixel electrode as a second plate of said capacitor, wherein said pixel electrode is laterally positioned such that it is offset in a vertical direction from said gate electrode and such that it overlaps in a vertical direction with said first plate and at least a gate electrode of a thin film transistor for driving a neighbouring pixel of the active matrix optoelectronics device.
2. An electronic structure as claimed in claim 1 further comprising a via between said second plate and a drain pad coupled to said drain, said via being connected substantially centrally to a surface of said drain pad.
3. An electronic structure as claimed in claim 2 wherein said via is laterally positioned so as to pass through said first plate in a vertical direction.
4. A multilayer electronic structure as claimed in claim 1 wherein a plurality of dielectric layers is provided between said first and second conducting layers.
5. A multilayer electronic structure as claimed in claim 4 wherein a nearer one of the plurality of dielectric layers to an active region of said thin film transistor for driving a pixel has a lower dielectric constant than a farther one of the plurality of dielectric layers.
6. An electronic structure as claimed in claim 1 wherein said thin film transistor comprises an organic semiconductor material.
7. An electronic structure as claimed in claim 6 wherein the electronic structure is adapted to solution deposition.
8. An electronic structure as claimed in claim 1 wherein said substrate comprises a flexible substrate.
9. A pixel drive structure for an active matrix display including the multilayer electronic structure of claim 1 wherein said second plate of said capacitor comprises a pixel drive electrode for driving a pixel of said display.
10. A pixel drive structure as claimed in claim 9 wherein said first plate of said capacitor is connected to a reference potential line or interconnect of said pixel drive structure.
11. An active matrix display comprising a plurality of lines of pixel drive structures as claimed in claim 9 , and a plurality of source lines disposed substantially parallel and alternating to said lines of pixel drive structures, wherein said neighbouring pixel is a neighbour in a same one of said lines of pixel drive structures.
12. An active matrix display as claimed in claim 9 wherein second plates of each line of pixel drive structures are positioned such that they planarly overlap with a corresponding adjacent one of the source lines.
13. A method of fabricating a multilayer electronic structure on a substrate, the method comprising:
depositing and patterning a first conducting layer over said substrate to define source and drain electrodes of a thin film transistor for driving a pixel of an active matrix optoelectronics device;
depositing an organic semiconducting layer over said first conducting layer;
depositing a first dielectric layer over said organic semiconducting layer;
depositing and patterning a first portion of a second conducting layer over said first dielectric layer to define a gate electrode of said thin film transistor;
depositing and patterning a second portion of said second conducting layer substantially coplanar to said first portion to define a first plate of a capacitor for storing charge to maintain an electrical state of said active matrix pixel;
depositing a second dielectric layer over said second conducting layer;
depositing and patterning a third conducting layer over said second dielectric layer to define a second plate of said capacitor;
wherein said second plate is laterally positioned such that it is offset in a vertical direction from said gate electrode and such that it overlaps in a vertical direction with said first plate and at least a gate electrode of a thin film transistor for driving a neighbouring pixel of the active matrix optoelectronics device.
14. A method of fabricating a multilayer electronic structure as claimed in claim 13 wherein said depositing and patterning a first conducting layer over said substrate further defines a drain pad coupled to said drain.
15. A method of fabricating a multilayer electronic structure as claimed in claim 14 wherein, prior to depositing and patterning said third conducting layer, the method further comprises forming a via to said drain pad, and wherein said via is formed such that it connects substantially centrally to an upper surface of said drain pad.
16. A method of fabricating a multilayer electronic structure as claimed in claim 13 wherein a plurality of dielectric layers is deposited between said organic semiconducting layer and second conducting layer.
17. A method of fabricating a multilayer electronic structure as claimed in claim 13 wherein a plurality of dielectric layers is deposited between said second and third conducting layers.
18. A method of fabricating a multilayer electronic structure as claimed in claim 16 wherein relative to said organic semiconducting layer, a nearer one of the plurality of dielectric layers has a lower dielectric constant than a farther one of the plurality of dielectric layers.
19. A method of fabricating a multilayer electronic structure as claimed in claim 13 wherein at least some of said deposition and patterning steps employ a solution processing technique.
20. A method of fabricating an active matrix display comprising fabricating a structure for substantially each of a plurality of pixels of said display as claimed in the method of claim 13 .