Phase locked loop

1. A phase locked loop comprising:

a tuneable oscillator;

a mixer-based phase sensitive detector to receive input signals from the tuneable oscillator and a reference signal;

a cycle slip detector to receive input signals from the tuneable oscillator and the reference signal, the cycle slip detector being configured to generate an output signal when two consecutive pulses are present in one of its input signals without an intervening pulse in the other of its input signals;

coarse tune signal means to receive the output signal generated by the cycle slip detector;

adding means for adding a signal output by the coarse tune signal means to a signal output by the phase sensitive detector to control the frequency of the tuneable oscillator;

disabling means for selectively disabling the signal output by the phase sensitive detector; and

enabling means comprising a timer for enabling the signal output by the phase sensitive detector.

2. A phase locked loop according to claim 1 wherein the enabling means is configured to measure a time interval between adjacent output signals of the cycle slip detector.

3. A phase locked loop according to claim 2 wherein the enabling means is configured to compare the time interval so measured to a threshold and to enable the signal output by the phase sensitive detector when the time interval betters the threshold.

4. A phase locked loop according to claim 1 further comprising a frequency translation stage for translating the frequency of the signal output by the tuneable oscillator to a different frequency.

5. A phase locked loop according to claim 1 wherein the cycle slip detector is configured to generate a first output signal indicating that the frequency of the signal output by the tuneable oscillator should be increased when the two consecutive pulses are present in the reference signal and is configured to generate a second output signal indicating that the frequency of the signal output by the tuneable oscillator should be decreased when the two consecutive pulses are present in the tuneable oscillator signal.

6. A phase locked loop according to claim 5 wherein the coarse tune signal means is configured to increment its output signal when it receives the first output signal from the cycle slip detector as an input and is configured to decrease its output signal when it receives the second output signal from the cycle slip detector as its input signal.

7. A phase locked loop comprising:

a tuneable oscillator;

a mixer-based phase sensitive detector to receive input signals from the tuneable oscillator and a reference signal;

a cycle slip detector to receive input signals from the tuneable oscillator and the reference signal, the cycle slip detector being configured to generate an output signal when two consecutive pulses are present in one of its input signals without an intervening pulse in the other of its input signals;

coarse tune signal means to receive the output signal generated by the cycle slip detector, wherein the coarse tune signal means comprises a register and a digital to analogue converter, and wherein an output step of the digital to analogue converter is selected so as to bring about a change in the frequency of the output signal of the tuneable oscillator of approximately 50% of the loop bandwidth; and

adding means for adding a signal output by the coarse tune signal means to a signal output by the phase sensitive detector to control the frequency of the tuneable oscillator.