Memory buffer for buffer-on-board applications

1. An apparatus, comprising:

a memory buffer that is compatible with a Joint Electron Devices Engineering Council (JEDEC) standard, wherein the memory buffer includes:

a decoder that receives an input command signal as its input and generates a first output command signal as its output;

a register component that receives the input command signal as its input and generates a second output command signal as its output; and

a multiplexer that receives a control signal as its control input and receives both the first output command signal and the second output command signal as its data input, wherein the control signal configures the multiplexer to operate in one of a JEDEC decode mode in which the multiplexer routes the first output command signal to the output of the multiplexer, and a proprietary decode mode in which the multiplexer routes the second output command signal to the output of the multiplexer.

2. The apparatus of claim 1 , wherein:

the input command signal is received from a central processing unit (CPU) and is selected from the group consisting of: a chip-select input signal, a clock-enable input signal, and an on-die termination input signal;

the first output command signal is selected from the group consisting of: a plurality of first chip-select output signals, a plurality of first clock-enable output signals, and a plurality of first on-die termination output signals; and

the second output command signal is selected from the group consisting of: a plurality of second chip-select output signals, a plurality of second clock-enable output signals, and a plurality of second on-die termination output signals.

3. The apparatus of claim 1 , wherein the first output command signal contains a different bit pattern from the second output command signal.

4. The apparatus of claim 1 , wherein:

the input command signal includes an N number of bits, N being an integer;

the register component includes the N number of BitMap registers that each contain a plurality of bit fields; and

each bit of the input command signal is coupled to a respective one of the BitMap registers so as to serve as an enable input to that BitMap register.

5. The apparatus of claim 4 , wherein the register component generates the second output command signal by programming the bit fields in response to a desired configuration of a downstream memory device.

6. The apparatus of claim 1 , wherein the first and second output command signals each contain twice as many bits as the input command signal.

7. The apparatus of claim 1 , further including an output alignment component coupled to the output of the multiplexer, wherein the output alignment component is operable to adjust a timing delay of one of: the first output command signal and the second output command signal.

8. A method, comprising:

generating, using a decoder, a first output command signal in response to an input command signal;

generating, using a register component, a second output command signal in response to the input command signal; and

selecting one of the first output command signal and the second output command signal to be outputted in response to a control signal, wherein the selecting is carried out so that the first output command signal is selected if the control signal indicates that a standard Joint Electron Devices Engineering Council (JEDEC) decode mode is chosen, and the second output command signal is selected if the control signal indicates that a proprietary decode mode is chosen.

9. The method of claim 8 , wherein:

the generating the first output command signals includes mapping the input command signal to the first output command signal according to a predetermined decoding table; and

the generating the second output command signal includes programming arbitrary values into the register component in response to an optimization priority.

10. The method of claim 9 , wherein the decoder and the register component are implemented on a memory buffer compatible with a JEDEC standard, and wherein the decoding table is a JEDEC decoding table that determines how a chip-select signal, a clock-enable signal, and an on-die termination signal should be mapped from an input to the memory buffer to the output of the memory buffer.

11. The method of claim 10 , wherein:

if the optimization priority is optimization for memory performance, then the generating the second output command signal includes programming the register component in a manner so as to remap the chip-select signal, the clock-enable signal, and the on-die termination signal for a highest rank interleave across a plurality of downstream memory devices that are coupled to the memory buffer;

if the optimization priority is optimization for power consumption, then the generating the second output command signal includes programming the register component in a manner so as to remap the chip-select signal, the clock-enable signal, and the on-die termination signal to support maximum clock-enable power down and self-refresh granularity across the plurality of downstream memory devices; and

if the optimization priority is optimization for reliability/availability/serviceability, then the generating the second output command signal includes programming the register component in a manner so as to remap the chip-select signal, the clock-enable signal, and the on-die termination signal to keep consecutive ranks on the same downstream memory devices.

12. The method of claim 8 , wherein:

the input command signal includes an N number of bits, N being an integer;

the register component includes N number of BitMap registers that each contain a plurality of bit fields; and

each bit of the input command signal is coupled to a respective one of the BitMap registers so as to serve as an enable input to that BitMap register.

13. The method of claim 8 , further including:

outputting the selected one of the first and second output command signals to an alignment component; and

adjusting, using the alignment component, a timing delay of the selected one of the first and second output command signals.

14. A digital apparatus, comprising:

a decoder component that maps an input command signal to a first output command signal according to a predefined decoding table;

means for mapping the input command signal to a second output command signal; and

a multiplexer that selects either the first output command signal or the second output command signal to be outputted in response to a control signal, wherein the first output command signal is selected if the control signal indicates that a standard Joint Electron Devices Engineering Council (JEDEC) decode mode is chosen, and the second output command signal is selected if the control signal indicates that a proprietary decode mode is chosen.

15. The digital apparatus of claim 14 , wherein the means for mapping the input command signal includes a plurality of registers that each contain a plurality of programmable bit fields, and wherein values of the bit fields are programmed to achieve a desired optimization scheme.

16. The digital apparatus of claim 14 , wherein:

the decoding table is a decoding table according to a JEDEC standard;

the input command signal is received from an upstream memory controller and includes one of: a chip-select input signal, a clock-enable input signal, and an on-die termination input signal; and

the first and second output command signals contain different bit patterns.