Semiconductor device
View Patent ↗The semiconductor device includes a first wiring; a second wiring; a third wiring; a fourth wiring; a first transistor having a first gate electrode, a first source electrode, and a first drain electrode; and a second transistor having a second gate electrode, a second source electrode, and a second drain electrode. The first transistor is formed on or in a substrate including a semiconductor material. The second transistor includes an oxide semiconductor layer.
1. A semiconductor device comprising:
a source line;
a bit line;
a first signal line;
a plurality of second signal lines;
a plurality of word lines;
a plurality of memory cells connected in series between the source line and the bit line;
a driver circuit configured to drive the plurality of second signal lines and the plurality of word lines so as to select a memory cell specified by an address signal;
a writing circuit configured to output a writing potential to the first signal line;
a reading circuit configured to compare a plurality of reading potentials and a bit line potential input from the bit line connected to the specified memory cell;
a control circuit configured to select any of a plurality of compensation voltages in response to a comparison result of the bit line potential and the plurality of reading potentials; and
a potential generation circuit configured to generate the writing potential and the plurality of reading potentials to be supplied to the writing circuit and the reading circuit,
wherein one of the plurality of memory cells comprises:
a first transistor having a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and
a capacitor,
wherein a substrate including a semiconductor material is provided with the first transistor,
wherein the second transistor includes an oxide semiconductor layer, and
wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other,
wherein the source line and the first source electrode are electrically connected to each other,
wherein the bit line and the first drain electrode are electrically connected to each other,
wherein the first signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other,
wherein one of the plurality of second signal lines and the second gate electrode are electrically connected to each other,
wherein one of the plurality of word lines and the other of the electrodes of the capacitor are electrically connected to each other, and
wherein the oxide semiconductor layer is formed using an In—Ga—Zn—O-based oxide semiconductor material.
2. A semiconductor device comprising:
a source line;
a bit line;
a first signal line;
a plurality of second signal lines;
a plurality of word lines;
a plurality of memory cells connected in series between the source line and the bit line;
a driver circuit configured to drive the plurality of second signal lines and the plurality of word lines so as to select a memory cell specified by an inputted address signal;
a writing circuit configured to output a first writing potential to the first signal line in a first writing operation, and output any of a plurality of second writing potentials to the first signal line in a second writing operation;
a reading circuit configured to read data of the specified memory cell by comparing a first bit line potential input from the bit line connected to the specified memory cell and a plurality of first reading potentials in a first reading operation, and comparing a second bit line potential input from the bit line connected to the specified memory cell and a plurality of second reading potentials in a second reading operation;
a control circuit configured to select any of a plurality of compensation voltages in response to a comparison result of the first bit line potential and the plurality of first reading potentials, and select any of the plurality of second writing potentials; and
a potential generation circuit configured to generate the first writing potential, the plurality of second writing potentials, the plurality of first reading potentials, and the plurality of second reading potentials to be supplied to the writing circuit and the reading circuit,
wherein one of the plurality of memory cells comprises:
a first transistor having a first gate electrode, a first source electrode, and a first drain electrode;
a second transistor having a second gate electrode, a second source electrode, and a second drain electrode; and
a capacitor,
wherein a substrate including a semiconductor material is provided with the first transistor,
wherein the second transistor includes an oxide semiconductor layer, and
wherein the first gate electrode, one of the second source electrode and the second drain electrode, and one of electrodes of the capacitor are electrically connected to each other,
wherein the source line and the first source electrode are electrically connected to each other,
wherein the bit line and the first drain electrode are electrically connected to each other,
wherein the first signal line and the other of the second source electrode and the second drain electrode are electrically connected to each other,
wherein one of the plurality of second signal lines and the second gate electrode are electrically connected to each other,
wherein one of the plurality of word lines and the other of the electrodes of the capacitor are electrically connected to each other, and
wherein the oxide semiconductor layer is formed using an In—Ga—Zn—O-based oxide semiconductor material.
3. The semiconductor device according to claim 1 , further comprising:
a first selection line;
a second selection line;
a third transistor having a gate electrode electrically connected to the first selection line; and
a fourth transistor having a gate electrode electrically connected to the second selection line,
wherein the bit line is electrically connected to the first drain electrode through the third transistor, and
wherein the source line is electrically connected to the first source electrode through the fourth transistor.
4. The semiconductor device according to claim 1 , wherein the first transistor includes a channel formation region provided in the substrate including the semiconductor material, impurity regions provided so as to sandwich the channel formation region, a first gate insulating layer over the channel formation region, the first gate electrode over the first gate insulating layer, and the first source electrode and the first drain electrode electrically connected to the impurity regions.
5. The semiconductor device according to claim 1 , wherein the second transistor includes the second gate electrode over the substrate including the semiconductor material, a second gate insulating layer over the second gate electrode, the oxide semiconductor layer over the second gate insulating layer, and the second source electrode and the second drain electrode electrically connected to the oxide semiconductor layer.
6. The semiconductor device according to claim 1 , wherein the substrate including the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.
7. The semiconductor device according to claim 1 , wherein the semiconductor material is silicon.
8. The semiconductor device according to claim 1 , wherein the oxide semiconductor layer includes a crystal of In 2 Ga 2 ZnO 7 .
9. The semiconductor device according to claim 1 , wherein concentration of hydrogen in the oxide semiconductor layer is 5×10 19 atoms/cm 3 or less.
10. The semiconductor device according to claim 1 , wherein an off-state current of the second transistor is 1×10 −13 A or less.
11. A semiconductor device comprising:
a source line;
a bit line;
a first memory cell and a second memory cell connected in series between the source line and the bit line;
a first signal line electrically connected to the first memory cell and the second memory cell;
two second signal lines, one of the two second signal lines electrically connected to the first memory cell, the other of the two second signal lines electrically connected to the second memory cell;
two word lines, one of the two word lines electrically connected to the first memory cell, the other of the two word lines electrically connected to the second memory cell;
a driver circuit electrically connected to the two second signal lines and the two word lines, and configured to select a memory cell specified by an inputted address signal;
a writing circuit configured to output a writing potential to the first signal line;
a reading circuit configured to compare a plurality of reading potentials and a bit line potential input from the bit line connected to the specified memory cell;
a control circuit configured to select any of a plurality of compensation voltages in response to a comparison result of the bit line potential and the plurality of reading potentials; and
a potential generation circuit configured to generate the writing potential and the plurality of reading potentials to be supplied to the writing circuit and the reading circuit,
wherein each of the first memory cell and the second memory cell comprises at least one transistor comprising an oxide semiconductor layer, and
wherein the oxide semiconductor layer is formed using an In—Ga—Zn—O-based oxide semiconductor material.
12. A semiconductor device comprising:
a source line;
a bit line;
a first memory cell and a second memory cell connected in series between the source line and the bit line;
a first signal line electrically connected to the first memory cell and the second memory cell;
two second signal lines, one of the two second signal lines electrically connected to the first memory cell, the other of the two second signal lines electrically connected to the second memory cell;
two word lines, one of two the word lines electrically connected to the first memory cell, the other of the two word lines electrically connected to the second memory cell;
a driver circuit electrically connected to the two second signal lines and the two word lines, and configured to select the first memory cell or the second memory cell specified by an inputted address signal;
a writing circuit configured to output a first writing potential to the first signal line in a first writing operation, and output any of a plurality of second writing potentials to the first signal line in a second writing operation;
a reading circuit configured to read data of the specified memory cell by comparing a first bit line potential input from the bit line connected to the specified memory cell and a plurality of first reading potentials in a first reading operation, and comparing a second bit line potential input from the bit line connected to the specified memory cell and a plurality of second reading potentials in a second reading operation;
a control circuit configured to select any of a plurality of compensation voltages in response to a comparison result of the first bit line potential and the plurality of first reading potentials, and select any of the plurality of second writing potentials; and
a potential generation circuit configured to generate the first writing potential, the plurality of second writing potentials, the plurality of first reading potentials, and the plurality of second reading potentials to be supplied to the writing circuit and the reading circuit,
wherein each of the first memory cell and the second memory cell comprises a first transistor and a second transistor,
wherein the second transistor includes a channel region comprising an oxide semiconductor layer, and
wherein the oxide semiconductor layer is formed using an In—Ga—Zn—O-based oxide semiconductor material.
13. The semiconductor device according to claim 12 , further comprising a capacitor,
wherein the first transistor is formed on or in a substrate including a semiconductor material,
wherein a gate electrode of the first transistor is electrically connected to the capacitor, and
wherein one of a source electrode or a drain electrode of the second transistor is electrically connected to the gate electrode of the first transistor.
14. The semiconductor device according to claim 13 , wherein the substrate including the semiconductor material is a single crystal semiconductor substrate or an SOI substrate.
15. The semiconductor device according to claim 13 , wherein the semiconductor material is silicon.
16. The semiconductor device according to claim 13 , wherein the oxide semiconductor layer includes a crystal of In 2 Ga 2 ZnO 7 .
17. The semiconductor device according to claim 13 , wherein concentration of hydrogen in the oxide semiconductor layer is 5×10 19 atoms/cm 3 or less.
18. The semiconductor device according to claim 13 , wherein an off-state current of the second transistor is 1×10 −13 A or less.