Manufacturing semiconductor devices

1. A method of manufacturing a semiconductor device, the method comprising:

alternately forming insulating interlayers and sacrificial layers on a substrate, the insulating interlayers and the sacrificial layers having a first opening exposing the substrate;

forming a semiconductor pattern in the first opening, the semiconductor pattern contacting the substrate and protruding above an uppermost insulating interlayer;

forming a second opening through the insulating interlayers and the sacrificial layers, the second opening exposing a portion of the substrate adjacent to the semiconductor pattern;

forming grooves among the insulating interlayers by selectively removing the sacrificial layers, the grooves partially exposing sidewalls of the semiconductor pattern;

forming gate structures in the grooves, respectively;

forming a common source line in the second opening, the common source line contacting the substrate and protruding above the uppermost insulating interlayer;

forming an etch stop layer pattern on the semiconductor pattern wherein the semiconductor pattern protrudes above the uppermost insulating interlayer and on the common source line and wherein the common source line protrudes above the uppermost insulating interlayer;

forming an additional insulating interlayer on the uppermost insulating interlayer; and

forming contact plugs through the additional insulating interlayer, the contact plugs contacting the semiconductor pattern and the common source line, respectively.

2. The method as claimed in claim 1 , wherein the etch stop layer pattern is formed using silicon nitride.

3. The method as claimed in claim 1 , further comprising forming a buffer layer on the uppermost insulating interlayer, the semiconductor pattern, and the common source line before forming the etch stop layer pattern.

4. The method as claimed in claim 1 , wherein forming the etch stop layer pattern comprises:

forming an etch stop layer on the uppermost insulating interlayer, the semiconductor pattern, and the common source line; and

partially etching the etch stop layer to form the etch stop layer pattern on sidewalls of the semiconductor pattern and the common source line.

5. The method as claimed in claim 1 , wherein the etch stop layer pattern is formed on the uppermost insulating interlayer, the semiconductor pattern, and the common source line.

6. The method as claimed in claim 1 , wherein forming the common source line comprises:

forming an insulation layer filling the second opening;

partially etching the insulation layer in the second opening to form an insulation layer pattern on a sidewall of the second opening; and

forming a conductive layer to fill the second opening.

7. The method as claimed in claim 1 , further comprising doping impurities into an upper portion of the semiconductor pattern.

8. The method as claimed in claim 1 , wherein forming the semiconductor pattern comprises:

forming a semiconductor layer on a sidewall of the first opening;

forming a filling layer on the semiconductor layer to fill the first opening;

partially removing the semiconductor layer and the filling layer to form a first semiconductor pattern and a filling layer pattern in the first opening, wherein the first semiconductor pattern is lower than an upper end of the first opening; and

forming a second semiconductor pattern on the first semiconductor pattern and the filling layer pattern.

9. The method as claimed in claim 1 , wherein forming the gate structures comprises:

forming a tunnel insulation layer, a charge storing layer, and a blocking dielectric layer on the grooves in the second opening;

forming a conductive layer on the blocking dielectric layer; and

partially removing the conductive layer to form control gates in the grooves.

10. A method of forming a memory device having a plurality of gate structures arranged in a vertical string, the method comprising:

forming a plurality of laterally-extending conductive control gates, each of the control gates extending from a respective gate structure of the vertical string;

forming an uppermost insulating interlayer, the uppermost insulating interlayer covering the plurality of control gates;

forming a vertical channel, the vertical channel including a vertical semiconductor pattern that corresponds to the gate structures and is proximate to the control gates, the vertical semiconductor pattern being formed to extend through the uppermost insulating interlayer such that a portion of the vertical semiconductor pattern is exposed by the uppermost insulating interlayer;

forming a vertical common source line, the common source line being parallel to the vertical channel, the common source line being separated from the gate structures by an insulation layer pattern;

forming an etch stop layer pattern, the etch stop layer pattern being formed to cover the portion of the vertical semiconductor pattern and cover at least a portion of the uppermost insulating interlayer adjacent to the portion of the vertical semiconductor pattern;

forming an additional insulating interlayer on the uppermost insulating interlayer;

forming a first contact hole through the uppermost additional insulating interlayer using an etching process, the first contact hole being formed in a position corresponding to the portion of the vertical semiconductor pattern;

forming a second contact hole through the additional insulating interlayer using an etching process, the second contact hole being formed in a position cones corresponding to the common source line;

forming a bit line contact in the first contact hole such that the bit line contact is electrically connected to the portion of the vertical semiconductor pattern; and

forming a contact plug in the second contact hole such that the contact plug is electrically connected to the common source line.

11. The method as claimed in claim 10 , further comprising forming a bit line, the bit line being formed on the bit line contact such that the bit line is electrically connected to the bit line contact.

12. The method as claimed in claim 10 , wherein the common source line is disposed between vertical strings such that gate structures are adjacent to the common source line on at least two sides thereof, and the etch stop layer pattern is formed to have spacer-shaped elements disposed alongside the common source line and over portions of the gate structures that are adjacent to the common source line.

13. The method as claimed in claim 12 , wherein the etch stop layer pattern is formed to have spacer-shaped elements disposed alongside the vertical semiconductor pattern, the spacer-shaped elements being disposed over portions of the gate structures that are adjacent to the bit line contact and over portions of the control gates that are adjacent to the vertical semiconductor pattern.