Integrated Non-Linearity (INL) and Differential Non-Linearity (DNL) correction techniques for digital-to-analog converters (DACS)

1. A method for use with a digital-to-analog converter (DAC), the method comprising:

(a) accepting an N bit digital input code at an input of the DAC;

(b) selecting a first correction code from a first set of correction codes based on a portion of the N bit digital input code, wherein the first set of correction codes are used to reduce to a range of Integrated Non-Linearity (INL) values, to thereby improve linearity of the DAC;

(c) selecting a second correction code from a second set of correction codes based on a portion of the N bit digital input code, wherein the second set of correction codes are used to ensure that all values of Differential Non-Linearity (DNL)>−1, and thereby ensure that the DAC is monotonic;

(d) producing an N+M bit digital output code based on the N bit digital input code accepted at step (a), the first correction code selected at step (b), and the second correction code selected at step (c); and

(e) converting the N+M bit digital output code to an analog output signal, wherein the analog output signal or a buffered version thereof is the analog output of the DAC.

2. The method of claim 1 , wherein M=1.

3. The method of claim 1 , wherein:

step (b) comprises selecting the first correction code from the first set of correction codes based on a predetermined number of the most significant bits (MSBs) of the N bit digital input code; and

step (c) comprises selecting the second correction code from the second set of correction codes based on the predetermined number of the most significant bits (MSBs) of the N bit digital input code.

4. The method of claim 3 , wherein:

the converting at step (e) is performed by an N+M bit DAC that comprises a plurality of segments, including a most significant segment and a least significant segment;

the most significant segment includes 2^X sub-segments implemented by resistors; and

the portions of the N-bit digital input code, used by the code corrector to select the first and second correction codes from the first and second LUTs, comprise the X MSBs of the N-bit digital input code.

5. The method of claim 1 , wherein step (d) comprises:

(d.1) adding the first correction code selected at step (b) to the N bit digital input code accepted at step (a) to produce an N bit INL corrected code (INLCC);

(d.2) bit extending the N bit INLCC to produce an N+M bit INLCC;

(d.3) determining whether the N+M bit INLCC requires DNL correction;

(d.4) if the N+M bit INLCC requires DNL correction, then modifying the N+M bit INLCC based on a scaled version of the second correction code selected at step (c), to thereby produce the N+M bit digital output code; and

(d.5) if the N+M bit INLCC does not require DNL correction, then having the N+M bit digital output code equal to the N+M bit INLCC.

6. The method of claim 1 , wherein:

M≧1; and

step (d) includes using the M bit(s) of additional resolution to remap at least some of 2^N possible digital input codes that can be accepted at the input of the DAC to ensure that all values of DNL>−1.

7. The method of claim 1 , wherein:

M≧1; and

wherein step (d) includes using the M bit(s) of additional resolution to compress codes prior to and/or after one or more codes that if uncorrected result in a DNL<−1.

8. The method of claim 1 , further comprising:

determining and storing the first and second sets of correction codes during off-line testing of the DAC.

9. A device, comprising:

a code corrector adapted to

accept an N bit digital input code;

select a first correction code from a first set of correction codes based on a portion of the N bit digital input code, wherein the first set of correction codes are used to reduce to a range of Integrated Non-Linearity (INL) values;

select a second correction code from a second set of correction codes based on a portion of the N bit digital input code, wherein the second set of correction codes are used to ensure that all values of Differential Non-Linearity (DNL)>−1; and

produce a N+M bit digital output code based on the accepted N bit digital input code, the selected first correction code, and the selected second correction code; and

an N+M bit DAC adapted to accept the N+M bit digital code output by the code corrector and output an analog signal based on the accepted N+M bit digital code.

10. The device of claim 9 , wherein the code corrector includes:

a first look-up table (LUT) adapted to store the first set of correction codes; and

a second look-up table (LUT) adapted to store the second set of correction codes.

11. The device of claim 10 , wherein the code corrector is adapted to:

select the first correction code from the first LUT based on a predetermined number of the most significant bits (MSBs) of the N bit digital input code, and

select the second correction code from the second LUT based on the predetermined number of the MSBs of the N bit digital input code.

12. The device of claim 11 , wherein the code corrector is adapted to:

add the first correction code selected from the first LUT to the accepted N bit digital input code to produce an N bit INL corrected code (INLCC);

bit extend N bit INLCC to produce an N+M bit INLCC;

determine whether the N+M bit INLCC requires DNL correction;

modify the N+M bit INLCC based on a scaled version of the second correction code selected from the second LUT, if the N+M bit INLCC requires DNL correction; and

have the N+M bit digital output code equal to the N+M bit INLCC, if the N+M bit INLCC does not require DNL correction.

13. The device of claim 11 , wherein the first LUT and the second LUT are stored in non-volatile memory that is part of or otherwise accessible by the code corrector.

14. The device of claim 13 , wherein X=4.

15. The device of claim 9 , wherein the N+M bit DAC comprises:

a plurality of segments, including a most significant segment and a least significant segment;

wherein the most significant segment includes 2^X sub-segments implemented by resistors; and

wherein the portions of the N-bit digital input code, used by the code corrector to select the first and second correction codes from the first and second LUTs, comprise the X MSBs of the N-bit digital input code.

16. The device of claim 9 , wherein M=1.

17. A device, comprising:

a code corrector adapted to

store and/or access a first set of correction codes used to reduce to a range of Integrated Non-Linearity (INL) values;

store and/or access a second set of correction codes used to ensure that all values of Differential Non-Linearity (DNL)>−1;

select a first correction code from the first set of correction codes based on a portion of an N bit digital input code;

select a second correction code from the second set of correction codes based on a portion of the N bit digital input code; and

produce an N+M bit digital output code based on the N bit digital input code, the selected first correction code, and the selected second correction code; and

an N+M bit DAC adapted to accept the N+M bit digital code output by the code corrector and output an analog signal based on the accepted N+M bit digital code.

18. The device of claim 17 , wherein the code corrector is adapted to:

add the first correction code to the N bit digital input code to produce an N bit INL corrected code (INLCC);

bit extend the N bit INLCC to produce an N+M bit INLCC;

modify the N+M bit INLCC based on a scaled version of the second correction code, if the N+M bit INLCC requires DNL correction; and

have the N+M bit digital output code equal to the N+M bit INLCC, if the N+M bit INLCC does not require DNL correction.

19. The device of claim 17 , wherein the first and second sets of correction codes are stored in non-volatile memory that is part of or otherwise accessible by the code corrector.

20. The device of claim 17 , further comprising:

a buffer adapted to receive the analog signal output by the N+M bit DAC;

wherein an output of the buffer comprises an output of the device.