IP Library Granted Patent US 8,564,583
Granted Patent B2
US 8,564,583 · App. 12/640,180 · Granted Oct 22, 2013

Bias circuit for a complementary current mode logic drive circuit

Inventors: Kevin Yikai Liang (Fremont, CA); Xin Liu (El Dorado Hill, CA); Arvind Bomdica (Fremont, CA); Ming-Ju Edward Lee (San Jose, CA)
Assignee: Advanced Micro Devices, Inc.
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Quick Facts
Patent No.
US 8,564,583
App. No.
12/640,180
Granted
Oct 22, 2013
Kind
B2
Abstract

A circuit includes a complementary current mode logic driver circuit and a dual feedback current mode logic bias circuit. The complementary current mode logic driver circuit provides a first output voltage and a second output voltage. The dual feedback current mode logic bias circuit includes a first feedback circuit and a second feedback circuit. The first feedback circuit provides a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage. The second feedback circuit provides a second bias voltage in response to the second output voltage.

Claims (48)

1. A circuit comprising:

a complementary current mode logic driver circuit that is operative to provide a first output voltage and a second output voltage; and

a dual feedback current mode logic bias circuit comprising:

a first feedback circuit that is operative to provide a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage; and

a second feedback circuit that is operative to provide a second bias voltage for the complementary current mode logic driver circuit in response to the second output voltage.

2. The circuit of claim 1 wherein the first feedback circuit has a first bandwidth and the second feedback circuit has a second bandwidth that is less than the first bandwidth.

3. The circuit of claim 1 wherein:

the first feedback circuit comprises a first differential amplifier circuit that is operative to provide the first bias voltage in response to the first output voltage; and

the second feedback circuit comprises a second differential amplifier circuit that is operative to provide the second bias voltage in response to the second output voltage.

4. The circuit of claim 3 wherein the first differential amplifier circuit has a first bandwidth and the second differential amplifier circuit has a second bandwidth that is less than the first bandwidth.

5. The circuit of claim 1 further comprising a voltage reference circuit that is operative to provide a first reference voltage and a second reference voltage, wherein the first feedback circuit that is operative to provide the first bias voltage based on the first reference voltage and the second feedback circuit is operative to provide the second bias voltage based on the second reference voltage.

6. The circuit of claim 1 wherein:

the first feedback circuit comprises a first filter circuit, having a first pole, that is operative provide the first bias voltage in response to the first output voltage; and

the second feedback circuit comprises a second filter circuit, having a second pole, that is operative provide the second bias voltage in response to the second output voltage.

7. The circuit of claim 1 wherein the complementary current mode logic driver circuit is operative to provide a differential voltage based on the first bias voltage and the second bias voltage.

8. The circuit of claim 7 wherein:

the first output voltage corresponds to one of a first voltage of the differential voltage and a common mode voltage of the complementary current mode logic driver circuit; and

the second output voltage corresponds to one of a second voltage of the differential voltage and the common mode voltage of the complementary current mode logic driver circuit.

9. A device comprising:

a complementary current mode logic driver circuit that is operative to provide a first output voltage and a second output voltage;

a dual feedback current mode logic bias circuit comprising:

a first feedback circuit that is operative to provide a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage; and

a second feedback circuit that is operative to provide a second bias voltage for the complementary current mode logic driver circuit in response to the second output voltage; and

a display that is operative to display an image based on the first output voltage and the second output voltage.

10. The device of claim 9 wherein the first feedback circuit has a first bandwidth and the second feedback circuit has a second bandwidth that is less than the first bandwidth.

11. The device of claim 9 wherein:

the first feedback circuit comprises a first differential amplifier circuit that is operative to provide the first bias voltage in response to the first output voltage; and

the second feedback circuit comprises a second differential amplifier circuit that is operative to provide the second bias voltage in response to the second output voltage.

12. The device of claim 11 wherein the first differential amplifier circuit has a first bandwidth and the second differential amplifier circuit has a second bandwidth that is less than the first bandwidth.

13. The device of claim 9 further comprising a voltage reference circuit that is operative to provide a first reference voltage and a second reference voltage, wherein the first feedback circuit that is operative to provide the first bias voltage based on the first reference voltage and the second feedback circuit is operative to provide the second bias voltage based on the second reference voltage.

14. The device of claim 9 wherein:

the first feedback circuit comprises a first filter circuit, having a first pole, that is operative provide the first bias voltage in response to the first output voltage; and

the second feedback circuit comprises a second filter circuit, having a second pole, that is operative provide the second bias voltage in response to the second output voltage.

15. The device of claim 9 wherein the complementary current mode logic driver circuit is operative to provide a differential voltage based on the first bias voltage and the second bias voltage.

16. The device of claim 15 wherein:

the first output voltage corresponds to one of a first voltage of the differential voltage and a common mode voltage of the complementary current mode logic driver circuit; and

the second output voltage corresponds to one of a second voltage of the differential voltage and the common mode voltage of the complementary current mode logic driver circuit.

17. A non-transitory computer readable medium comprising information that when executed by at least one processor causes the at least one processor to:

at least one of: operate, design, and organize a circuit that comprises:

a complementary current mode logic driver circuit that is operative to provide a first output voltage and a second output voltage; and

a dual feedback current mode logic bias circuit comprising:

a first feedback circuit that is operative to provide a first bias voltage for the complementary current mode logic driver circuit in response to the first output voltage; and

a second feedback circuit that is operative to provide a second bias voltage for the complementary current mode logic driver circuit in response to the second output voltage.

18. The computer readable medium of claim 17 wherein the first feedback circuit has a first bandwidth and the second feedback circuit has a second bandwidth that is less than the first bandwidth.

19. The computer readable medium of claim 17 wherein:

the first feedback circuit comprises a first differential amplifier circuit that is operative to provide the first bias voltage in response to the first output voltage; and

the second feedback circuit comprises a second differential amplifier circuit that is operative to provide the second bias voltage in response to the second output voltage.

20. The computer readable medium of claim 17 wherein the information comprises data representing hardware description language.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 25, 2021
From: SILICON STORAGE TECHNOLOGY, INC.
To: ZENO SEMICONDUCTOR, INC.
Reel/Frame 056681/0744 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 8, 2010
From: LIANG, KEVIN YIKAI; LIU, XIN; BOMDICA, ARVIND; LEE, MING-JU EDWARD
To: ADVANCED MICRO DEVICES, INC.
Reel/Frame 024044/0226 →
Continuity (1)
Related Publication 20110148838A1 · Jun 23, 2011