IP Library Granted Patent US 8,570,021
Granted Patent B2
US 8,570,021 · App. 12/815,126 · Granted Oct 29, 2013

DC/DC converter having a delay generator circuit positioned between a comparator and a pulse generator and a DC/DC converter control method

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Quick Facts
Patent No.
US 8,570,021
App. No.
12/815,126
Granted
Oct 29, 2013
Kind
B2
Abstract

A DC/DC converter includes a first comparator configured to compare an output voltage to a reference voltage; a pulse generator circuit configured to generate a pulse signal when triggered by an output signal from the first comparator; a first switch circuit configured to open and close on the basis of the pulse signal; an output voltage generator configured to generate the output voltage on the basis of an input voltage supplied via the first switch circuit; a delay generator circuit configured to delay the output signal from the first comparator before outputting; and an error amplifier configured to control a delay time of the delay generator circuit on the basis of a potential difference between the output voltage and the reference voltage.

Claims (26)

1. A DC/DC converter, comprising:

a first comparator configured to compare an output voltage to a reference voltage;

a pulse generator circuit configured to generate a pulse signal when triggered by an output signal from the first comparator;

a first switch circuit configured to open and close on the basis of the pulse signal;

an output voltage generator configured to generate the output voltage on the basis of an input voltage supplied via the first switch circuit;

a delay generator circuit positioned between the first comparator and the pulse generator circuit, the delay generator circuit being configured to delay the output signal from the first comparator before outputting the output signal from the first comparator to the pulse generator circuit; and

an error amplifier configured to control a delay time of the delay generator circuit on the basis of a potential difference between the output voltage and the reference voltage.

2. The DC/DC converter according to claim 1 , wherein the delay generator circuit includes:

a charging current controller configured to control a charging current on the basis of an output signal from the error amplifier;

a delay-setting unit configured to repeat a capacitor charging operation using the charging current from the charging current controller and configured to repeat a capacitor discharging operation, on the basis of the output signal from the first comparator; and

a second comparator configured to compare the charging voltage of the capacitor to a reference voltage.

3. The DC/DC converter according to claim 2 , wherein the delay generator circuit includes:

a charging current controller configured to add current to the charging current in accordance with the input voltage; and

a reference voltage generator configured to generate a reference voltage that limits the delay time to a maximum delay time set by the delay-setting unit and configured to then output the reference voltage to the second comparator, on the basis of the potential difference between the input voltage and the output voltage.

4. The DC/DC converter according to claim 2 , wherein the delay-setting unit includes:

a flip-flop circuit configured to receive the output signal from the first comparator at its set terminal and the output signal from the second comparator at its reset terminal; and

a second switch circuit configured to open and close according to the output signal from the flip-flop circuit and to cause accumulated charge in the capacitor to be discharged when in the conducting state.

5. The DC/DC converter according to claim 1 , wherein the pulse generator circuit causes the first switch circuit to enter a conducting state when triggered by a falling edge of the output signal from the first comparator.

6. The DC/DC converter according to claim 1 , wherein the pulse generator circuit causes the first switch circuit to enter a non-conducting state when triggered by a rising edge of the output signal from the first comparator.

7. A DC/DC converter control method, comprising:

generating a pulse signal when triggered by a comparison result obtained by comparing an output voltage to a reference voltage;

opening or closing a switch circuit on the basis of the pulse signal; and

generating the output voltage on the basis of an input voltage supplied via the switch circuit,

wherein the pulse signal is generated using a delay signal that delays the comparison result on the basis of the potential difference between the output voltage and the reference voltage.

8. The DC/DC converter control method according to claim 7 , wherein the switch circuit enters a conducting state when triggered by a falling edge of an output signal obtained by comparing the output voltage to the reference voltage.

9. The DC/DC converter control method according to claim 7 , wherein the switch circuit enters a non-conducting state when triggered by a rising edge of an output signal obtained by comparing the output voltage to the reference voltage.

Assignments (8)
MERGER Recorded Nov 14, 2025
From: CYPRESS SEMICONDUCTOR CORPORATION
To: INFINEON TECHNOLOGIES AMERICAS CORP.
Reel/Frame 073571/0456 →
RELEASE OF SECURITY INTEREST Recorded Mar 16, 2022
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
Reel/Frame 059410/0438 →
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036052/0016 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2013
From: FUJITSU SEMICONDUCTOR LIMITED
To: SPANSION LLC
Reel/Frame 031205/0461 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 16, 2010
From: YOSHINO, TAKAHIRO
To: FUJITSU SEMICONDUCTOR LIMITED
Reel/Frame 024545/0638 →