IP Library Granted Patent US 8,618,461
Granted Patent B2
US 8,618,461 · App. 13/771,148 · Granted Dec 31, 2013

Solid-state imaging device and imaging device

Inventor: Hirotaka Doi (Osaka, JP)
Assignee: Panasonic Corporation
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Quick Facts
Patent No.
US 8,618,461
App. No.
13/771,148
Granted
Dec 31, 2013
Kind
B2
Abstract

A solid-state imaging device includes a plurality of AD conversion units respectively provided in a plurality of columns and each configured to convert a pixel signal converted by unit pixels provided in an associated column into digital data of N bits, and a plurality of data storage units respectively provided in the columns. The data storage units each include N flip-flop circuits. The solid-state imaging device further includes data switching units each configured to switch between a first state in which the digital data converted by the AD conversion unit is stored in the data storage unit of the associated column, and a second state in which the N flip-flop circuits in each of the data storage units are serially connected.

Claims (46)

1. A solid-state imaging device, comprising:

a plurality of unit pixels that each converts incident light into a pixel signal, the unit pixels being arranged in rows and columns;

a plurality of AD conversion units respectively provided in a plurality of columns and each configured to convert the pixel signal converted by the unit pixel located in an associated column into digital data of N bits, N being an integer not smaller than 2; and

a plurality of data storage units respectively provided in the plurality of columns,

wherein the data storage units each include N flip-flop circuits respectively corresponding to bits of the digital data of N bits,

the solid-state imaging device further comprising:

a plurality of data switching units each configured to switch between:

a first state in which the digital data of N bits converted by the AD conversion unit is stored in the data storage unit of the associated column; and

a second state in which the N flip-flop circuits included in each of the data storage units are serially connected.

2. The solid-state imaging device according to claim 1 ,

wherein the data switching units are configured to switch among the first state, the second state, and a third state in which the data storage units respectively provided in the plurality of columns are serially connected.

3. The solid-state imaging device according to claim 2 , comprising

a plurality of column blocks each associated with a column unit including a predetermined number of columns, and each including a plurality of the AD conversion units and a plurality of the data storage units, the AD conversion units and the data storage units being associated with the column unit,

wherein the data switching units are configured to serially connect, in each of the column blocks, the data storage units in the column block in the third state.

4. The solid-state imaging device according to claim 3 ,

Wherein the data switching units are configured to serially connect, in each of the column blocks, all of the flip-flop circuits in the column block in the second state.

5. The solid-state imaging device according to claim 1 , further comprising

a control unit configured to control the data storage units and the data switching units,

wherein the control unit is configured to:

store the digital data of N bits converted by the AD conversion unit in the data storage unit of the associated column after setting the data switching units to the first state; and

amplify the digital data stored in the data storage unit by shifting each bit of the digital data toward a high-order bit, after setting the data switching units to the second state.

6. The solid-state imaging device according to claim 2 ,

wherein the data switching units are configured to serially connect, in the second state, the flip-flop circuits each located at a first stage of the N flip-flop circuits serially connected in the associated column, in the same sequence as in the third state.

7. The solid-state imaging device according to claim 1 ,

wherein the data switching units each include a logic level switching unit configured to output, in the second state, a signal of a first logical value to the flip-flop circuit at a first stage of the N flip-flop circuits serially connected.

8. The solid-state imaging device according to claim 7 ,

wherein the logic level switching unit is configured to selectively output, in the second state, one of the signal of the first logical value and a signal of a second logical value to the flip-flop circuit at the first stage.

9. The solid-state imaging device according to claim 3 ,

wherein the data switching units each include a logic level switching unit configured to output, in the third state, a signal of a first logical value to the data storage unit at a first stage of the data storage units serially connected.

10. The solid-state imaging device according to claim 9 ,

wherein the logic level switching unit is configured to selectively output, in the third state, one of the signal of the first logical value and a signal of a second logical value to the data storage unit at the first stage.

11. The solid-state imaging device according to claim 10 ,

wherein the logic level switching unit is further configured to selectively output, in the second state, one of the signal of the first logical value and the signal of the second logical value to the flip-flop circuit at the first stage of the N flip-flop circuits serially connected.

12. The solid-state imaging device according to claim 2 , further comprising

a control unit configured to provide (i) a clock signal of a first frequency to the plurality of flip-flop circuits, after setting the data switching unit to the first state, and (ii) a clock signal of a second frequency lower than the first frequency to the flip-flop circuits, after setting the data switching unit to the second state.

13. The solid-state imaging device according to claim 12 ,

wherein the control unit is further configured to provide the clock signal of the first frequency to the flip-flop circuits, after setting the data switching unit to the third state.

14. The solid-state imaging device according to claim 1 , further comprising:

a defect information storage unit configured to store defect information indicating a data storage unit of which column has a defect, among the plurality of data storage units;

a redundant data storage unit; and

a redundant switching unit configured to replace the data storage unit of the column indicated by the defect information, with the redundant data storage unit.

15. The solid-state imaging device according to claim 1 , further comprising:

a defect information storage unit configured to store defect information indicating a flip-flop circuit of which column and which bit has a defect, among the plurality of flip-flop circuits;

a plurality of redundant flip-flop circuits respectively provided in the plurality of columns; and

a redundant switching unit configured to replace the flip-flop circuit of the column and the bit indicated by the defect information, with the redundant flip-flop circuit provided in the corresponding column.

16. An imaging device comprising the solid-state imaging device according to claim 1 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 4, 2013
From: DOI, HIROTAKA
To: PANASONIC CORPORATION
Reel/Frame 031343/0053 →
Priority Claims (1)
JP 2010-200372 · Sep 7, 2010 · national
Continuity (2)
Continuation PCTJP2011004641 · Aug 19, 2011
Related Publication 20130161488A1 · Jun 27, 2013