Controlling method and controller for memory

1. A memory controlling method, for controlling a memory comprising a command transmission port and a data transmission port, the method comprising:

detecting whether an error condition occurs in an electronic device associated with the memory the electronic device, including confirming the error condition according to a debounce condition; and

sending an interrupt command to the memory via the command transmission port when the error condition is detected, for stopping an operation of the memory associated with the data transmission port.

2. The method according to claim 1 , further comprising repeating the detecting step when it is determined that the error condition does not occur.

3. The method according to claim 1 , wherein the error condition is a voltage failure or a system crash.

4. The method according to claim 1 , wherein the memory is a secure digital (SD) card.

5. The method according to claim 1 , wherein the debounce condition is associated with a power supply feature of the electronic device.

6. The method according to claim 1 , wherein the sending the interrupt command step comprises:

determining when to send the interrupt command at a sending time via the command transmission port.

7. The method according to claim 1 , wherein the interrupt command is a stop reading/writing command or a memory stop command.

8. The method according to claim 1 , wherein the detecting step further comprises:

determining whether the operation associated with the data transmission port is under execution; and

determining the error condition occurs when it is determined that the operation associated with the data transmission port is under execution.

9. The method according to claim 8 , further comprising:

determining the error condition occurs when it is determined that the operation associated with the data transmission port is not under execution.

10. A memory controller, for controlling a memory comprising a command transmission port and a data transmission port different from the command transmission port, the controller comprising:

a detection module, for detecting an error condition in an electronic device associated with the memory, the detection module being configured to confirm the error condition according to a debounce condition; and

a protection module, coupled to the detection module, for sending an interrupt command to the memory via the command transmission port of the memory, so as to stop an operation of the memory associated with the data transmission port in response to the error condition.

11. The memory controller according to claim 10 , wherein the error condition is a voltage interrupt or a system crash.

12. The memory controller according to claim 10 , wherein the memory is a secure digital (SD) card.

13. The memory controller according to claim 10 , wherein the debounce condition is associated with a power supply feature of the electronic device.

14. The memory controller according to claim 10 , wherein when the detection module detects the error condition, the protection module determines when to send the interrupt command at a sending time via the command transmission port.

15. The memory controller according to claim 10 , wherein the interrupt command is a stop reading/writing command or a memory stop command.

16. The memory controller according to claim 10 , wherein the detection module is a voltage detector or a mechanical sensor.

17. A memory controller, operative with a memory comprising a command transmission port and a data transmission different from the command transmission port, the controller comprising:

a detection module, for detecting whether an error condition occurs in an electronic device associated with the memory, and for confirming the error condition according to a debounce condition; and

a protection module, for determining whether an operation associated with the data transmission port is being performed when the detection module detects the error condition, and when it is determined that the operation is being performed, sending an interrupt command to the memory via the command transmission port to stop the operation of the memory associated with the data transmission port.