Low-current logic plus driver circuit

1. A circuit, comprising:

a logic stage that includes a current limiter comprising a D-mode feedback transistor having a source, a drain, a gate and a gate-source junction, the current limiter further comprising a component that generates a voltage drop and a feedback loop connecting the source of the D-mode feedback transistor to the gate of the D-mode feedback transistor via the component that generates the voltage drop;

an inverter stage coupled to the logic stage and including a further current limiter comprising a further D-mode feedback transistor having a source, a drain, a gate and a gate-source junction, the further current limiter further comprising a further component that generates a voltage drop, and a further feedback loop connecting the source of the further D-mode feedback transistor to the gate of the further D-mode feedback transistor via the further component that generates the voltage drop; and

a driver stage coupled to the inverter stage and comprising E-mode transistors having a source, a drain and a gate, the E-mode transistors being connected in a totem pole.

2. The circuit of claim 1 , wherein the D-mode feedback transistors are not conducting between the source and the drain if a gate-source voltage that is applied between the gate and the source is more negative than a negative threshold voltage, and are conducting between the source and the drain otherwise, and wherein the E-mode transistors are conducting between the source and the drain if a gate-source voltage that is applied between the gate and the source is more positive than a positive threshold voltage, and are not conducting between the source and the drain otherwise.

3. The circuit of claim 1 , further comprising at least one further E-mode transistor having a gate-source junction and/or a gate-drain junction generating the voltage drop in at least one of the current limiters.

4. The circuit according to claim 1 , wherein the component that generates the voltage drop in at least one of the current limiters comprises at least two gate-source junctions of further E-mode transistors, the gate-source junctions being connected in series.

5. The circuit according to claim 1 , wherein the inverter stage comprises a further E-mode transistor having a source, a drain and a gate, the further E-mode transistor coupled to the further current limiter.

6. The circuit according to claim 5 , wherein the component that generates the voltage drop in at least one of the current limiters comprises at least two gate-source junctions of further E-mode transistors, the gate-source junctions being connected in series.

7. The circuit according to claim 6 , wherein the drain of the further E-mode transistor of the inverter stage is connected with the gate of one of the E-mode transistors of the driver stage, and wherein the gate of the further E-mode transistor of the inverter stage is connected with the gate of another one of the E-mode transistors of the driver stage.

8. The circuit according to claim 4 , further comprising a diode coupled between a supply voltage and the gate of one of the E-mode transistors of the driver stage.

9. The circuit according to claim 1 , wherein the inverter stage inverts a logic signal from the logic stage, changing the signal from high to low or from low to high, and wherein the driver stage renders a low output signal if the signal from the inverter stage is low, and a high output signal if the signal from the inverter stage is high.

10. The circuit according to claim 1 , wherein an output signal of the driver stage is used to switch a load circuit.

11. The circuit according to claim 9 , further comprising:

a further D-mode transistor having a source, a drain, and a gate; and

a further E-mode transistor having a source, a drain, and a gate;

wherein the load circuit is coupled between the drain of the further E-mode transistor and the source of the further D-mode transistor; and

wherein the driver stage is connected to the gates of the further D-mode transistor and the further E-mode transistor.

12. The circuit according to claim 1 , wherein the transistors are devices of a P-HEMT or BiFET technology in GaAs.

13. A circuit comprising:

a combinational logic circuit having a plurality of logic inputs, a first reference terminal and a second reference terminal;

a first D-mode transistor having a source, a drain and a gate, the gate coupled to the second reference terminal of the combinational logic circuit;

a first component that generates a voltage drop having a first terminal coupled to the source of the first D-mode transistor and a second terminal coupled to the second reference terminal of the combinational logic circuit;

a first E-mode transistor having a source, a drain and a gate, the gate coupled to the second reference terminal of the combinational logic circuit and the source coupled to the first reference terminal of the combinational logic circuit;

a second D-mode transistor having a source, a drain and a gate, the gate coupled to the drain of the first E-mode transistor and the drain coupled to the drain of the first D-mode transistor;

a second component that generates a voltage drop having a first terminal coupled to the source of the second D-mode transistor and a second terminal coupled to the drain of the first E-mode transistor;

a second E-mode transistor having a source, a drain and a gate, the gate coupled to the drain of the first E-mode transistor and the drain coupled to the drains of the first and second D-mode transistors; and

a third E-mode transistor having a source, a drain and a gate, the gate coupled to the gate of the first E-mode transistor, the source coupled to the source of the first E-mode transistor and the first reference terminal of the combinational logic circuit, and the drain coupled to the source of the second E-mode transistor.

14. The circuit according to claim 13 , wherein the circuit is implemented with GaAs.

15. The circuit according to claim 13 , wherein the first reference terminal of the combinational logic circuit, the source of the first E-mode transistor and the source of the third E-mode transistor are coupled to a ground node and wherein the drains of the first and second D-mode transistors and the drain of the second E-mode transistor are coupled to a supply voltage node.

16. The circuit according to claim 13 , wherein:

the first component that generates the voltage drop comprises a fourth E-mode transistor having a source, a drain and a gate, the gate being the first terminal and the source being the second terminal; and

the second component that generates the voltage drop comprises a fifth E-mode transistor having a source, a drain and a gate, the gate being the first terminal and the source being the second terminal.

17. The circuit according to claim 13 , wherein:

the first component that generates the voltage drop comprises a fourth E-mode transistor having a source, a drain and a gate, the gate being the first terminal of the first component; and

a sixth E-mode transistor having a source, a drain and a gate, the source being the second terminal of the first component, wherein the gate of the sixth E-mode transistor is coupled to the source of the fourth E-mode transistor; and

the second component that generates the voltage drop comprises a fifth E-mode transistor having a source, a drain and a gate, the gate being the first terminal of the second component; and

a seventh E-mode transistor having a source, a drain and a gate, the source being the second terminal of the second component, wherein the gate of the seventh E-mode transistor is coupled to the source of the fifth E-mode transistor.

18. The circuit according to claim 13 , further comprising a diode with a first terminal coupled to the drains of the first and second D-mode transistors and the drain of the second E-mode transistor and a second terminal coupled to the gate of the second E-mode transistor.

19. The circuit according to claim 13 , further comprising:

a third D-mode transistor having a source, a drain and a gate, the drain coupled to the drains of the first and second D-mode transistors and the gate coupled to the source of the second E-mode transistor and the drain of the third E-mode transistor; and

an eighth E-mode transistor having a source, a drain and a gate, the gate coupled to the gate of the third D-mode transistor and the source coupled to the sources of the first and third E-mode transistors.

20. The circuit according to claim 19 , further comprising a load coupled between the source of the third D-mode transistor and the drain of the eighth E-mode transistor.

21. A circuit using GaAs technology, the circuit comprising:

a combinational logic circuit having a plurality of logic inputs, a first reference terminal and a second reference terminal;

a first D-mode transistor having a source, a drain and a gate, the gate coupled to the second reference terminal of the combinational logic circuit;

a fourth E-mode transistor having a source, a drain and a gate, the gate coupled to source of the first D-mode transistor;

a sixth E-mode transistor having a source, a drain and a gate, the source being coupled to the second reference terminal of the combinational logic circuit;

a first E-mode transistor having a source, a drain and a gate, the gate coupled to the second reference terminal of the combinational logic circuit and the source coupled to the first reference terminal of the combinational logic circuit;

a second D-mode transistor having a source, a drain and a gate, the gate coupled to the drain of the first E-mode transistor and the drain coupled to the drain of the first D-mode transistor;

a fifth E-mode transistor having a source, a drain and a gate, the gate being coupled to the source of the second D-mode transistor;

a seventh E-mode transistor having a source, a drain and a gate, the source being coupled to the drain of the first E-mode transistor;

a second E-mode transistor having a source, a drain and a gate, the gate coupled to the drain of the first E-mode transistor and the drain coupled to the drains of the first and second D-mode transistors;

a third E-mode transistor having a source, a drain and a gate, the gate coupled to the gate of the first E-mode transistor, the source coupled to the source of the first E-mode transistor and the first reference terminal of the combinational logic circuit, and the drain coupled to the source of the second E-mode transistor;

a diode with a first terminal coupled to the drains of the first and second D-mode transistors and the drain of the second E-mode transistor and a second terminal coupled to the gate of the second E-mode transistor;

a third D-mode transistor having a source, a drain and a gate, the drain coupled to the drains of the first and second D-mode transistors and the gate coupled to the source of the second E-mode transistor and the drain of the third E-mode transistor; and

an eighth E-mode transistor having a source, a drain and a gate, the gate coupled to the gate of the third D-mode transistor and the source coupled to the sources of the first and third E-mode transistors.