Driving circuit and driving method for display device

1. A driving circuit for a display apparatus in which the number of outputs from a gate driver that drives gate lines of a display panel is greater than the number of display lines of the display panel in the vertical direction, wherein

a gate start pulse signal for a next frame is output at (m−n+k+1)-th line from a beginning of a display period for a previous frame where m denotes the number of the display lines, n denotes the number of extra outputs from the gate driver at a side from which the scan is performed, k denotes a positive integer of at least 1, and a scan of the gate driver is performed from a side at which there is an extra output from the gate driver;

k pulses of a gate driver clock signal are output during a vertical blank period;

input of a gate driver clock signal is restarted from a beginning of a display period for the next frame; and

the gate start pulse signal is generated in response to a display data enable signal,

the driving circuit comprising:

an internal reference signal generation circuit that receives the display data enable signal and generates an internal reference signal having a same period as the display data enable signal;

a V line counter that counts the number of pulses included in the internal reference signal;

a V blank decision circuit that recognizes a vertical blank period by determining whether there is the display data enable signal and generates a V blank decision signal that remains active during the vertical blank period;

a comparison unit that outputs a control signal when a count value of said V line counter reaches (m−n+k+1);

a VSP generation circuit that generates a gate start pulse signal when receiving the control signal;

a VCK termination decision circuit that causes a VCK termination signal to become active when the count value of said V line counter reaches (m+k+1) and causes the VCK termination signal to become inactive when the V blank decision signal becomes inactive; and

a VCK generation circuit that generates a gate driver clock signal in response to the internal reference signal only when the VCK termination signal is inactive.

2. A display apparatus comprising:

a driving circuit according to claim 1 ; and

a display panel that is driven by the driving circuit.

3. A driving circuit for a display apparatus in which the number of outputs from a gate driver that drives gate lines of a display panel is greater than the number of display lines of the display panel in the vertical direction, wherein

a gate start pulse signal for a next frame is output at (m−n+k+1)-th line from a beginning of a display period for a previous frame where m denotes the number of the display lines, n denotes the number of extra outputs from the gate driver at a side from which the scan is performed, k denotes a positive integer of at least 1, and a scan of the gate driver is performed from a side at which there is an extra output from the gate driver;

k pulses of a gate driver clock signal are output during a vertical blank period;

input of a gate driver clock signal is restarted from a beginning of a display period for the next frame; and

the gate start pulse signal is generated in response to a horizontal synchronizing signal,

the driving circuit comprising:

an internal reference signal generation circuit that receives the horizontal synchronizing signal and generates an internal reference signal having the same period as the horizontal synchronizing signal;

a V line counter that counts the number of pulses included in the internal reference signal;

a V blank decision circuit that recognizes a vertical blank period based on a count value of said V line counter and generates a V blank decision signal that remains active during the vertical blank period;

a comparison unit that outputs a control signal when a count value of said V line counter reaches (m−n+k+1);

a VSP generation circuit that generates a gate start pulse signal when receiving the control signal;

a VCK termination decision circuit that causes a VCK termination signal to become active when the count value of said V line counter reaches (m+k+1) and causes the VCK termination signal to become inactive when the V blank decision signal becomes inactive; and

a VCK generation circuit that generates a gate driver clock signal in response to the internal reference signal only when the VCK termination signal is inactive.

4. A driving method of a display apparatus in which the number of outputs from a gate driver that drives gate lines of a display panel is greater than the number of display lines of the display panel in the vertical direction, the driving method comprises:

outputting a gate start pulse signal for a next frame at (m−n+k+1)-th line from a beginning of a display period for a previous frame where m denotes the number of the display lines, n denotes the number of extra outputs from the gate driver at a side from which the scan is performed, k denotes a positive integer of at least 1, and a scan of the gate driver is performed from a side at which there is an extra output from the gate driver;

outputting k pulses of a gate driver clock signal during a vertical blank period; and

restarting input of a gate driver clock signal from a beginning of a display period for the next frame,

wherein the gate start pulse signal is generated in response to a display data enable signal, and

the method further comprises:

receiving the display data enable signal and generating an internal reference signal having a same period as the display data enable signal;

counting the number of pulses included in the internal reference signal;

recognizing a vertical blank period by determining whether there is the display data enable signal and generating a V blank decision signal that remains active during the vertical blank period;

outputting a control signal when a count value of the pulses of the internal reference signal reaches (m−n+k+1);

generating a gate start pulse signal when receiving the control signal;

making a VCK termination signal to become active when the count value of the pulses of the internal reference signal reaches (m+k+1) and making the VCK termination signal to become inactive when the V blank decision signal becomes inactive; and

generating a gate driver clock signal in response to the internal reference signal only when the VCK termination signal is inactive.

5. A driving method of a display apparatus in which the number of outputs from a gate driver that drives gate lines of a display panel is greater than the number of display lines of the display panel in the vertical direction, the driving method comprises:

outputting a gate start pulse signal for a next frame at (m−n+k+1)-th line from a beginning of a display period for a previous frame where m denotes the number of the display lines, n denotes the number of extra outputs from the gate driver at a side from which the scan is performed, k denotes a positive integer of at least 1, and a scan of the gate driver is performed from a side at which there is an extra output from the gate driver;

outputting k pulses of a gate driver clock signal during a vertical blank period; and

restarting input of a gate driver clock signal from a beginning of a display period for the next frame,

wherein the gate start pulse signal is generated in response to a horizontal synchronizing signal, and the method further comprises:

receiving the horizontal synchronizing signal and generating an internal reference signal having the same period as the horizontal synchronizing signal;

counting the number of pulses included in the internal reference signal;

recognizing a vertical blank period based on a count value of the pulses of the internal reference signal and generating a V blank decision signal that remains active during the vertical blank period;

outputting a control signal when the count value of said pulses of the internal reference signal reaches (m−n+k+1);

generating a gate start pulse signal when receiving the control signal;

making a VCK termination signal to become active when the count value of said pulses of the internal reference signal reaches (m+k+1) and making the VCK termination signal to become inactive when the V blank decision signal becomes inactive; and

generating a gate driver clock signal in response to the internal reference signal only when the VCK termination signal is inactive.