Distributed PUF

1. An electronic system having a volatile memory with multiple memory locations, each specific memory location of the multiple memory locations being arranged to produce a respective value when powered up, the respective value depending on a physical, at least partially random, configuration of components constructing the specific memory location, wherein the electronic system comprises:

a key extraction means arranged to retrieve multiple values in a first order from the multiple memory locations and for determining a reproducible cryptographic key in dependency on the multiple values,

a re-ordering means in between the memory and the key extraction means for providing the multiple values to the key extraction means in a second order, different from the first order, prior to determining the cryptographic key, wherein

the memory comprises multiple separate memory blocks, and wherein the multiple memory locations are distributed over all the multiple memory blocks, the multiple separate memory blocks being distributed across an integrated circuit.

2. An electronic system as in claim 1 , wherein at least one of the multiple separate memory blocks comprises precisely one memory location.

3. An electronic system as in claim 1 , wherein the second order is arranged for permuting the multiple values across all the separate memory blocks.

4. An electronic system as in claim 1 , wherein each specific memory location of the multiple memory locations is associated in the key extracting means with a specific one of multiple addresses, the key extracting means being configured to retrieve, for determining the reproducible cryptographic key, the multiple values from the multiple memory locations through respective read requests for the respective addresses, the re-ordering means is arranged with an address decoder for reading in response to a specific one of the multiple read requests from a different memory location than the specific memory location associated with the specific address.

5. An electronic system as in claim 1 , wherein the electronic system comprises a helper data construction means, the helper data construction means being arranged to produce helper data in dependency on the multiple values and to store the helper data in helper data memory, and wherein the key extraction means is arranged to apply an error correcting procedure on the multiple values in dependency on the helper data for making the cryptographic key reproducible.

6. An electronic system as in claim 5 , comprising an unlock means coupled to the helper data construction means, wherein the helper data construction means is arranged to produce helper data upon the unlock means receiving an unlock signal.

7. An electronic system as in claim 5 , wherein the electronic system comprises a construction signaling means for signaling if the helper data has been created.

8. An electronic system as in claim 7 , wherein the construction signaling means includes a construction signaling flag arranged for indicating if the helper data has been created.

9. An electronic system as in claim 7 , wherein the construction signaling means comprises means for storing in the helper data memory a construction string which indicates that the helper data has been created.

10. An electronic system as in claim 1 wherein the memory is of a writable type and wherein the electronic system comprises an inversion means for writing to each of the specific memory locations an inverse of the specific value and inversion determination means for determining if the multiple memory locations store the inverse of the multiple values.

11. An electronic system as in claim 10 , wherein the inversion determination means comprises an inversion signaling flag for signaling that the multiple memory locations stores the inverse of the multiple values.

12. An electronic system as in claim 10 , wherein the electronic system comprises a helper data construction means, the helper data construction means being arranged to produce helper data in dependency on the multiple values and to store the helper data in helper data memory, and wherein the key extraction means is arranged to apply an error correcting procedure on the multiple values in dependency on the helper data for making the cryptographic key reproducible, and wherein the helper data construction means is further arranged for producing a verification string for indicating the correctness of the reproducible cryptographic key and storing the verification string in the helper data memory, wherein determining a reproducible cryptographic key in dependency on the multiple values selectably comprises inverting the multiple values, said selection depending on the verification string correctness indicating the correctness of the reproducible cryptographic key.

13. An electronic system as in claim 1 , wherein the electronic system is embodied in an integrated circuit.

14. An electronic system as in claim 1 , wherein the memory is a Static Random Access Memory (SRAM).

15. An electronic system as in claim 1 , wherein the memory comprises flip-flops.

16. An electronic system as in claim 1 , wherein at least one of the multiple memory blocks comprises a single flip-flop.

17. A method of determining a layout for an integrated circuit embodying an electronic system having a memory with multiple memory locations according to claim 1 , the method comprising

synthesizing a formal description of the integrated circuit to obtain a gate-level netlist of the integrated circuit, and

processing the netlist with a placement and routing tool to obtain the layout, wherein

processing the netlist comprises an obfuscation step wherein gates of the gate-level netlist are distributed randomly across the integrated circuit, the distributed gates including at least gates on which the respective values producible by the multiple memory locations depend.

18. A method of determining a reproducible cryptographic key, comprising:

(a) retrieving multiple values from multiple memory locations in a volatile memory, each specific memory location of the multiple memory locations being arranged to produce a specific one of multiple values when powered up, the specific value depending on a specific physical, at least partially random, configuration of specific components constructing the specific memory location,

(b) determining a reproducible cryptographic key in dependency on the multiple values, and

(c) re-ordering the multiple values prior to determining the cryptographic key.

19. A method of determining a reproducible cryptographic key as in claim 18 , comprising

constructing helper data in dependency on the multiple values,

storing the helper data in a helper data memory, and

signaling that the helper data has been created, wherein

determining the reproducible cryptographic key comprises applying an error correcting procedure on the multiple values in dependency on the helper data for making the cryptographic key reproducible.

20. A method of determining a reproducible cryptographic key as in claim 18 , comprising

writing to each of the specific memory locations an inverse of the specific value, and

determining if the multiple memory location store the inverse of the multiple values, wherein

the determining of the reproducible key comprises inverting the multiple values in dependency on the determining if the multiple memory location store the inverse of the multiple values.

21. A computer program comprising computer program code means adapted to perform all the steps of claim 17 when the computer program is run on a computer.

22. A computer program comprising computer program code means adapted to perform all the steps of claim 18 when the computer program is run on a computer.