IP Library Granted Patent US 8,710,421
Granted Patent B2
US 8,710,421 · App. 13/475,158 · Granted Apr 29, 2014

Solid-state imaging device and imaging apparatus

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Quick Facts
Patent No.
US 8,710,421
App. No.
13/475,158
Granted
Apr 29, 2014
Kind
B2
Abstract

A solid-state imaging device according to the present invention includes a pixel cell having a photodiode, a charge detection unit, an amplification transistor, a transfer transistor which transfers a signal charge to the charge detection unit in accordance with a transfer control signal, and a reset transistor which resets the charge detection unit in accordance with a reset control signal; a signal processing circuit which receives a pixel reset potential of the charge detection unit, and a pixel signal potential corresponding to the signal charge transferred to the charge detection unit; a charge pump circuit which steps up or steps down a potential of at least one of the transfer control signal and the reset control signal in accordance with a driving clock signal; and a control logic circuit which causes the driving clock signal to be stopped during a pixel reading time period.

Claims (33)

1. A solid-state imaging device, comprising:

a pixel cell including:

a light receiving unit configured to convert incident light to a signal charge,

a charge detection unit configured to convert, to a signal voltage, the signal charge transferred from said light receiving unit,

an amplification transistor which amplifies the signal voltage,

a transfer transistor which transfers, to said charge detection unit, the signal charge accumulated in said light receiving unit, in accordance with a transfer control signal, and

a reset transistor which resets a potential of said charge detection unit to a reset potential in accordance with a reset control signal;

a signal processing circuit which receives a pixel reset potential corresponding to the reset potential of said charge detection unit, and a pixel signal potential corresponding to the signal charge transferred to said charge detection unit;

a charge pump circuit which steps up or steps down a potential of at least one of the transfer control signal and the reset control signal in accordance with a driving clock signal; and

a control circuit which causes the driving clock signal to be stopped during a pixel reading time period in which the reset potential and the pixel signal potential are read.

2. The solid-state imaging device according to claim 1 ,

wherein said charge pump circuit steps up the potential of at least one of the transfer control signal and the reset control signal to a potential higher than a power source potential.

3. The solid-state imaging device according to claim 2 ,

wherein said pixel cell further includes a selection transistor which selects a pixel cell to be read, in accordance with a selection control signal, and

said charge pump circuit steps up a potential of the selection control signal.

4. The solid-state imaging device according to claim 2 , further comprising

a capacitive element connected to an output of said charge pump circuit.

5. The solid-state imaging device according to claim 1 ,

wherein said charge pump circuit steps down the potential of at least one of the transfer control signal and the reset control signal to a potential lower than a ground potential.

6. The solid-state imaging device according to claim 5 ,

wherein said pixel cell further includes a selection transistor which selects a pixel cell to be read, in accordance with a selection control signal, and

said charge pump circuit steps down a potential of the selection control signal.

7. The solid-state imaging device according to claim 5 , further comprising

a capacitive element connected to an output of said charge pump circuit.

8. The solid-state imaging device according to claim 3 ,

wherein the pixel reading time period is a time period in which said pixel cell is selected by said selection transistor.

9. The solid-state imaging device according to claim 1 ,

wherein said control circuit causes the driving clock signal to be stopped in a time period including a time interval from a time when said signal processing circuit receives the pixel reset potential to a time when said signal processing circuit receives the pixel signal potential.

10. The solid-state imaging device according to claim 1 , further comprising

a frequency multiplier circuit or a frequency divider circuit,

wherein the driving clock signal is generated by said frequency multiplier circuit or said frequency divider circuit.

11. An imaging apparatus comprising

the solid-state imaging device according to claim 1 .

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC CORPORATION
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0917 →