Integrated circuit testing with power collapsed
In examples, apparatus and methods are provided for an integrated circuit. The integrated circuit includes a first integrated circuit portion having a main power domain and a second integrated circuit portion having a collapsible power domain. The integrated circuit also has a level shifter having an input coupled to the second circuit portion and an output coupled to the first integrated circuit portion. The level shifter is configured to hold constant the level shifter output when power to the collapsible power domain is collapsed. A quiescent drain current measurement circuit can be coupled to test at least a part of the second integrated circuit portion. A boundary scan register can be coupled between the level shifter output and the first integrated circuit portion. The integrated circuit can also include a power management circuit.
1. An integrated circuit, comprising:
a first integrated circuit portion having a main power domain;
a second integrated circuit portion having a collapsible power domain; and
a level shifter having an input coupled to the second circuit portion and an output coupled to the first integrated circuit portion, wherein the level shifter is configured to hold constant the level shifter output to an output level based on a pre-collapse input from the collapsible power domain, when power to the collapsible power domain is collapsed.
2. The integrated circuit of claim 1 , further comprising a quiescent drain current measurement circuit coupled to test at least a part of the second integrated circuit portion.
3. The integrated circuit of claim 1 , wherein the level shifter has at least two output voltage levels.
4. The integrated circuit of claim 1 , further comprising a boundary scan register coupled between the level shifter output and the first integrated circuit portion.
5. The integrated circuit of claim 1 , further comprising a power management circuit configured to generate a level shifter control signal and an inverted version of the level shifter control signal, each being output to the level shifter via a respective boundary scan register.
6. The integrated circuit of claim 5 , further comprising a test access port coupled to control the power management circuit and the boundary scan registers.
7. The integrated circuit of claim 5 , wherein the power management circuit is configured to generate a port isolation signal.
8. The integrated circuit of claim 5 , wherein the power management circuit is configured to generate a memory isolation signal.
9. The integrated circuit of claim 5 , wherein the power management circuit is configured to generate a scan and test chain isolation signal.
10. The integrated circuit of claim 5 , wherein the power management circuit is configured to generate a single serial bus interface isolation signal.
11. The integrated circuit of claim 5 , wherein the power management circuit is configured to generate an off-chip memory interface isolation signal.
12. The integrated circuit of claim 1 , wherein the integrated circuit is integrated on a semiconductor die.
13. The integrated circuit of claim 1 , further comprising a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the integrated circuit is integrated.
14. A non-transitory computer-readable medium, comprising instructions stored thereon that, if executed by a lithographic device, cause the lithographic device to fabricate at least a part of a device, comprising:
a first integrated circuit portion having a main power domain;
a second integrated circuit portion having a collapsible power domain; and
a level shifter having an input coupled to the second circuit portion and an output coupled to the first integrated circuit portion, wherein the level shifter is configured to hold constant the level shifter output to an output level based on a pre-collapse input from the collapsible power domain, when power to the collapsible power domain is collapsed.
15. The non-transitory computer-readable medium of claim 14 , further comprising instructions stored thereon that, if executed by the lithographic device, cause the lithographic device to fabricate a quiescent drain current measurement circuit coupled to test at least a part of the second integrated circuit portion.
16. The non-transitory computer-readable medium of claim 14 , wherein the level shifter has at least two output voltage levels.
17. The non-transitory computer-readable medium of claim 14 , further comprising instructions stored thereon that, if executed by the lithographic device, cause the lithographic device to fabricate a boundary scan register coupled between the level shifter output and the first integrated circuit portion.
18. The non-transitory computer-readable medium of claim 14 , further comprising instructions stored thereon that, if executed by the lithographic device, cause the lithographic device to fabricate a power management circuit configured to generate a level shifter control signal and an inverted version of the level shifter control signal, each being output to the level shifter via a respective boundary scan register.
19. The non-transitory computer-readable medium of claim 14 , further comprising instructions stored thereon that, if executed by the lithographic device, cause the lithographic device to fabricate a test access port coupled to the control power management circuit and the boundary scan registers.
20. The non-transitory computer-readable medium of claim 14 , wherein the power management circuit is configured to generate a port isolation signal.
21. The non-transitory computer-readable medium of claim 14 , wherein the power management circuit is configured to generate a memory isolation signal.
22. The non-transitory computer-readable medium of claim 14 , wherein the power management circuit is configured to generate a scan and test chain isolation signal.
23. The non-transitory computer-readable medium of claim 14 , wherein the power management circuit is configured to generate a single serial bus interface isolation signal.
24. The non-transitory computer-readable medium of claim 14 , wherein the power management circuit is configured to generate an off-chip memory interface isolation signal.
25. A method for testing an integrated circuit having a first integrated circuit portion with a main power domain, a second integrated circuit portion having a collapsible power domain, and a level shifter having an input coupled to the second circuit portion and an output coupled to the first integrated circuit portion, comprising:
collapsing power to the collapsible power domain; and
holding constant, using the level shifter, the level shifter output to an output level based on a pre-collapse input from the collapsible power domain, when power to the collapsible power domain is collapsed.
26. The method of claim 25 , further comprising:
generating an isolation signal using a power manager; and
isolating the main power domain from the power-collapsible domain in response to the isolation signal.
27. The method of claim 26 , wherein the isolation signal comprises at least one of a freeze signal for isolating input-output ports of the integrated circuit, and a clamp signal for isolating a functional module of the integrated circuit.
28. The method of claim 26 , further comprising storing the isolation signal in a boundary scan register, and controlling the boundary scan register with a test controller.
29. The method of claim 25 , further comprising:
testing the power-collapsible domain when power is collapsed, using a test controller and a power manager.
30. The method of claim 29 , wherein the testing the power-collapsible domain comprises testing a power supply current.
31. An integrated circuit, comprising:
means for collapsing power to a collapsible power domain; and
means for holding, using a level shifter, a level shifter output constant to an output level based on a pre-collapse input from the collapsible power domain, when power to the collapsible power domain is collapsed.
32. The integrated circuit of claim 31 , further comprising:
means for generating an isolation signal; and
means for isolating a main power domain from the power-collapsible domain in response to the isolation signal.
33. The integrated circuit of claim 32 , wherein the isolation signal comprises at least one of a freeze signal for isolating input-output ports of the integrated circuit, and a clamp signal for isolating a functional module of the integrated circuit.
34. The integrated circuit of claim 32 , further comprising:
means for storing the isolation signal in a boundary scan register, and
means for controlling the boundary scan register.
35. The integrated circuit of claim 31 , further comprising:
means for testing the power-collapsible domain when power is collapsed.
36. The integrated circuit of claim 35 , wherein the testing the power-collapsible domain comprises testing a power supply current.
37. The integrated circuit of claim 35 , further comprising a device, selected from the group consisting of a set top box, music player, video player, entertainment unit, navigation device, communications device, personal digital assistant (PDA), fixed location data unit, and a computer, into which the integrated circuit is integrated.