Contact structure of semiconductor device

1. A contact structure for a semiconductor device comprising:

a substrate comprising a major surface and a cavity, the cavity having a bottom surface lower than the major surface;

a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and the strained material extends upward over the major surface of the substrate;

a first metal layer over the strained material;

a dielectric layer over the first metal layer, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and

a second metal layer over the dielectric layer.

2. The contact structure of claim 1 , wherein the strained material comprises SiGe, SiC, or SiP.

3. The contact structure of claim 1 , wherein the first metal layer comprises TiN or TaN.

4. The contact structure of claim 1 , wherein the dielectric layer comprises TiO 2 .

5. The contact structure of claim 1 , wherein the dielectric layer comprises Al 2 O 3 , NiO, or HfO 2 .

6. The contact structure of claim 1 , wherein the first metal layer has a thickness ranging from 1 nm to 3 nm.

7. The contact structure of claim 1 , wherein the second metal layer comprises Al, Ni, NiPt, or Pt.

8. A metal oxide semiconductor field effect transistor (MOSFET) comprising:

a substrate comprising a major surface and a cavity, the cavity having a bottom surface lower than the major surface;

a gate stack on the major surface of the substrate;

a shallow trench isolations (STI) region within the substrate, the cavity being between the STI region and the gate stack; and

a contact structure at least partially in the cavity, wherein the contact structure comprises:

a strained material in the cavity, wherein a lattice constant of the strained material is different from a lattice constant of the substrate, and the strained material extends upward over the major surface of the substrate;

a first metal layer over the strained material;

a dielectric layer over the first metal layer, wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm; and

a second metal layer over the dielectric layer.

9. The MOSFET of claim 8 , wherein the strained material comprises SiGe, SiC, or Sip.

10. The MOSFET of claim 8 , wherein the first metal layer comprises TiN or TaN.

11. The MOSFET of claim 8 , wherein the dielectric layer comprises TiO 2 .

12. The MOSFET of claim 8 , wherein the dielectric layer comprises Al 2 O 3 , NiO, or HfO 2 .

13. The MOSFET of claim 8 , wherein the first metal layer has a thickness ranging from 1 nm to 3 nm.

14. The MOSFET of claim 8 , wherein the second metal layer comprises Al, Ni, NiPt, or Pt.

15. A transistor, comprising:

a fin structure comprising a major surface and a cavity, the cavity having a bottom surface lower than the major surface;

a gate stack on the major surface of the fin structure; and

a contact structure comprising:

an epitaxially grown strained material in the cavity, wherein the strained material extends upward beyond the major surface,

a first metal layer over the strained material completely covering an upper surface of the strained material;

a dielectric layer over the first metal layer; and

a second metal layer over the dielectric layer.

16. The transistor of claim 15 , wherein the strained material comprises SiGe, SiC, or SiP.

17. The transistor of claim 16 , wherein

the first metal layer comprises TiN or TaN, and

the second metal layer comprises Al, Ni, NiPt, or Pt.

18. The transistor of claim 17 , wherein the dielectric layer comprises TiO 2 , Al 2 O 3 , NiO, or HfO 2 .

19. The transistor of claim 15 , wherein the dielectric layer has a thickness ranging from 1 nm to 10 nm.

20. The transistor of claim 15 , wherein the first metal layer has a thickness ranging from 1 nm to 3 nm.