Continuous graphics display method for multiple display devices during the processor non-responding period
The present invention provides an image/graphics data display mechanism for continuously displaying image/graphics data on multiple display devices of a computer that contains a system memory directly accessed by the computer's CPU during the CPU's power saving non-responding period, wherein there is provided sufficient system bandwidth, the mechanism of the present invention is independent on the resolution running on each display device and the number of display devices connected to the computer system. The mechanism provides two approaches to achieve continuous display of image/graphics data on multiple display devices computer system. In the first approach, a common clock source is used to coordinate display device horizontal synchronization signals, vertical synchronization signals, horizontal blank periods, and vertical blank periods. In the second approach, the mechanism has a control on the lengths and occurrences of the display device blank periods.
1. A graphics display method for continuously displaying a plurality of graphics data on multiple display devices of a computer system that contains a central processing unit (CPU) which has a memory controller inside the CPU, a graphics-processing unit coupled to the memory controller, and a system memory directly accessed by the CPU, wherein the display devices are coupled to the graphics-processing unit, the method comprising:
providing a common clock source to the display devices and synchronizing a plurality of blank periods of the display devices according to the common clock source, the plurality of blank periods of the display devices are in different frequencies;
receiving a power saving signal from the CPU, the power saving signal indicates a request for executing a power saving process by the CPU during a non-responding period of the CPU, so as to reduce consumptive power of the CPU, wherein memory access from the graphics-processing unit to the system memory through memory controller is blocked during the non-responding period of the CPU;
detecting an upcoming least common multiple occurrence of the blank periods of the display devices; and
executing the power saving process within the least common multiple occurrence, wherein the least common multiple occurrence is a period that the blank periods of all display devices occur at the same time.
2. The method of claim 1 , wherein the blank periods are a plurality of horizontal blank periods (HBPs).
3. The method of claim 2 , wherein the horizontal blank periods are provided by the graphics-processing unit.
4. The method of claim 1 , wherein the blank periods are a plurality of vertical blank periods (VBPs).
5. The method of claim 4 , wherein the vertical blank periods are provided by the graphics-processing unit.
6. A graphics display method for continuously displaying a plurality of graphics data on multiple display devices of a computer system that contains a central processing unit (CPU) which has a memory controller inside the CPU, a graphics-processing unit coupled to the memory controller, and a system memory directly accessed by the CPU, wherein the display devices are coupled to the graphics-processing unit, the method comprising:
providing a common clock source to the display devices and synchronizing a plurality of blank periods of the display devices according to the common clock source, the plurality of blank periods of the display devices are in different frequencies;
receiving a power saving signal from the CPU, the power saving signal indicates a request for executing a power saving process to make the CPU self-adjust a CPU-clock rate and a power level of the CPU during a non-responding period of the CPU, wherein memory access from the graphics-processing unit to the system memory through memory controller is blocked during the non-responding period of the CPU; detecting an upcoming least common multiple occurrence of the blank periods of the display devices; and
executing the power saving process within the least common multiple occurrence, wherein the least common multiple occurrence is a period that the blank periods of all display devices occur at the same time.
7. The method of claim 6 , wherein while executing the power saving process, the system memory is accessed by the CPU during the non-responding period of the CPU.