Dual clock edge triggered memory
View Patent ↗A memory circuitry includes memory components operable in response to first edges of an internal clock; and internal clock generating circuitry to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock.
1. Memory circuitry comprising:
memory components operable in response to first edges of an internal clock; and
internal clock generating circuitry configured to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock,
wherein read and write operations of the memory are triggered at the first edges.
2. The memory of claim 1 wherein the first edges are one of rising edges and falling edges.
3. The memory of claim 1 wherein the internal clock generating circuitry comprises:
a pulse generation circuit configured to generate a pulse in response to an edge of the system clock.
4. The memory of claim 3 wherein the internal clock generating circuit comprises an edge detection circuit to generate the first clock edges in response to the pulse.
5. The memory of claim 4 wherein the internal clock generating circuitry further comprises:
a hold circuit configured to receive the first clock edges from the edge detection circuit and hold a value to which the first edges transitions in response to the pulse.
6. The memory of claim 5 wherein the hold circuit is configured to hold a value of the internal clock until receipt of a reset signal.
7. The memory of claim 6 wherein the memory further comprises:
self-time circuitry, the self-time circuitry being configured to generate the reset signal pulse.
8. The memory of claim 3 wherein the edge detection circuit further comprises:
an enable input configured to receive an enable signal.
9. The memory of claim 1 wherein reset events of the memory are timed according to a self-timing circuitry.
10. The memory of claim 9 wherein the reset events are at least one of sense amplifier enable, bit line pre-charge on, word line off and clock generator reset.
11. The memory of claim 1 wherein the memory is a synchronous self-timed memory.
12. A system comprising:
at least one dual edge triggered synchronous component;
memory circuitry comprising:
memory components operable in response to first edges of an internal clock; and
internal clock generating circuitry configured to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock,
wherein read and write operations of the memory are triggered at the first edges.
13. The system of claim 12 wherein the at least one dual edge triggered synchronous component is a flip-flop.
14. The system of claim 12 wherein there is at least one combinational logic component.
15. Memory means comprising:
functional means for carrying out a memory function in response to first edges of an internal clock; and
clock generating means for generating the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock,
wherein read and write operations of the memory are triggered at the first edges of the internal clock.
16. The memory means of claim 15 wherein the clock generating means comprises:
pulse generating means for generating a pulse in response to an edge of the system clock.
17. The memory means of claim 16 wherein the clock generating means further comprises an edge detection circuit to generate the first clock edges in response to the pulse.
18. The memory means of claim 17 wherein the clock generating means comprises:
holding means for receiving the first clock edges from the edge detection means and holding a value to which the first edges transition in response to the pulse.
19. The memory means of claim 18 wherein the holding means is further for holding a value of the internal clock until receipt of a reset signal pulse.
20. The memory means of claim 19 wherein the memory means further comprises:
self-time means for generating the reset signal pulse.
21. The memory means of claim 17 wherein the edge detector means further comprises:
enable input means for receiving an enable signal.
22. The memory means of claim 15 wherein reset events of the memory are timed according to a self-timing circuitry.
23. The memory means of claim 22 wherein the reset events are at least one of sense amplifier enable, bit line pre-charge on, word line off and clock generator reset.
24. The memory means of claim 15 wherein the memory is a synchronous self-timed memory.
25. Memory circuitry comprising:
memory components operable in response to first edges of an internal clock; and
internal clock generating circuitry configured to generate the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock,
wherein reset events of the memory are timed according to a self-timing circuitry.
26. The memory of claim 25 wherein the reset events are at least one of sense amplifier enable, bit line pre-charge on, word line off and clock generator reset.
27. Memory means comprising:
functional means for carrying out a memory function in response to first edges of an internal clock; and
clock generating means for generating the internal clock in response to a system clock, wherein the first edges of the internal clock are generated in response to both a rising and a falling edge of the system clock,
wherein reset events of the memory are timed according to a self-timing circuitry.
28. The memory means of claim 27 wherein the reset events are at least one of sense amplifier enable, bit line pre-charge on, word line off and clock generator reset.