IP Library Granted Patent US 8,730,984
Granted Patent B2
US 8,730,984 · App. 13/099,215 · Granted May 20, 2014

Queuing based on packet classification

Inventors: Erik K. Mann (Hillsboro, OR); Patrick L. Connor (Portland, OR); Diamant Nimrod (Kiar Saba, IL)
Assignee: Intel Corporation
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Quick Facts
Patent No.
US 8,730,984
App. No.
13/099,215
Granted
May 20, 2014
Kind
B2
Abstract

A system includes a host and a network controller coupled to the host by a bus. The system includes logic to classify Transmission Control Protocol/Internet Protocol (TCP/IP) receive packets based on the network source, network destination, port source, and port destination of the respective receive packets; and cause queuing of the receive packets in a one of multiple receive queues based on the classifying such that receive packets having the same network source, network destination, port source, and port destination are to be queued to the same one of the multiple queues for processing.

Claims (56)

1. A method, comprising:

classifying respective Transmission Control Protocol/Internet Protocol (TCP/IP) receive packets based on a hash of a network source, a network destination, a TCP source port, and a TCP destination port of the respective TCP/IP receive packets;

store data in individual respective packet descriptors for individual respective TCP/IP receive packets, the individual respective packet descriptors each comprising an address of packet data in memory; and

causing queuing of respective entries for the respective TCP/IP receive packets in a one of multiple receive queues based on the classifying such that respective TCP/IP receive packets having the same network source, network destination, TCP source port, and TCP destination port are queued to the same one of the multiple receive queues for TCP session updating based on the respective packet descriptors of the respective TCP/IP receive packets, the TCP session updating to comprise reassembly of TCP session segments.

2. The method of claim 1 ,

wherein the multiple receive queues comprise network controller queues.

3. The method of claim 1 ,

wherein the multiple receive queues comprise host memory queues.

4. The method of claim 1 ,

wherein the classifying and causing queuing comprises classifying and causing queuing by a network controller.

5. The method of claim 1 , further comprising determining a time to transfer the data of multiple receive packets to the host.

6. A non-transitory processor readable storage medium, comprising instructions that when executed cause a processor to:

classify respective Transmission Control Protocol/Internet Protocol (TCP/IP) receive packets based on the a hash of a network source, a network destination, a TCP source port, and a TCP destination port of the respective TCP/IP receive packets;

store data in individual respective packet descriptors for individual respective TCP/IP receive packets, the individual respective packet descriptors each comprising a memory address of packet data; and

cause queuing of respective entries for the respective TCP/IP receive packets in a one of multiple receive queues based on the classifying such that respective TCP/IP receive packets having the same network source, network destination, TCP source port, and TCP destination port destination are queued to the same one of the multiple receive queues for TCP session updating based on the respective packet descriptors of the respective TCP/IP receive packets, the TCP session updating to comprise reassembly of TCP session segments.

7. The processor readable storage medium of claim 6 ,

wherein the multiple receive queues comprise network controller queues.

8. The processor readable storage medium of claim 6 ,

wherein the multiple receive queues comprise host memory queues.

9. The processor readable storage medium of claim 6 , wherein the instructions that when executed cause a processor to classify and cause queuing comprises instructions that when executed cause a processor to classify and cause queuing by a network controller.

10. The processor readable storage medium of claim 6 , further comprising instructions that when executed cause a processor to determine a time to transfer the data of multiple receive packets to a host.

11. A network controller, comprising:

a bus interface configured to be coupled to a host;

an interface configured to be coupled to a network; and

logic to:

classify respective Transmission Control Protocol/Internet Protocol (TCP/IP) receive packets based on a hash of a network source, a network destination, a TCP source port, and a TCP destination port of the respective TCP/IP receive packets;

store data in individual respective packet descriptors for individual respective TCP/IP receive packets, the individual respective packet descriptors each comprising a memory address of packet data; and

cause queuing of respective entries for the respective TCP/IP receive packets in a one of multiple receive queues based on the classifying such that respective TCP/IP receive packets having the same network source, network destination, TCP source port, and TCP destination port are queued to the same one of the multiple receive queues for TCP session updating based on the respective packet descriptors of the respective TCP/IP receive packets, the TCP session updating to comprise reassembly of TCP session segments.

12. The network controller of claim 11 ,

wherein the multiple receive queues comprise network controller queues.

13. The network controller of claim 11 ,

wherein the multiple receive queues comprise host memory queues.

14. The network controller of claim 11 , further comprising logic to determine a time to transfer the data of multiple receive packets to the host.

15. A system, comprising:

a host; and

a network controller coupled to the host by a bus; and

logic to:

classify respective Transmission Control Protocol/Internet Protocol (TCP/IP) receive packets based on a hash of a network source, a network destination, a TCP source port, and a TCP destination port of the respective TCP/IP receive packets;

store data in individual respective packet descriptors for individual respective TCP/IP receive packets, the individual respective packet descriptors each comprising a memory address of packet data; and

cause queuing of respective entries for the respective TCP/IP receive packets in a one of multiple receive queues based on the classifying such that respective TCP/IP receive packets having the same network source, network destination, TCP source port, and TCP destination port are queued to the same one of the multiple receive queues for TCP session updating based on the respective packet descriptors of the respective TCP/IP receive packets, the TCP session updating to comprise reassembly of TCP session segments.

16. The system of claim 15 ,

wherein the multiple receive queues comprise network controller queues.

17. The system of claim 15 ,

wherein the multiple receive queues comprise host memory queues.

18. The system of claim 15 , further comprising logic to determine a time to transfer the data of multiple receive packets to the host.

19. A non-transitory processor readable storage medium, comprising instructions that when executed cause a host processor to:

access respective receive queues, the receive queues to store entries for respective Transmission Control Protocol/Internet Protocol (TCP/IP) receive packets based on a hash of a network source, a network destination, a TCP source port, and a TCP destination port of the respective TCP/IP receive packets wherein respective TCP/IP receive packets having the same network source, network destination, port source, and port destination are to be queued to the same one of the respective receive queues for processing, the receive packets to arrive via a host's network controller; and

perform TCP session updating by the host for the respective TCP/IP receive packets, the TCP session updating comprising reassembly of TCP session segments, the TCP session updating being based on data stored in individual packet descriptors for individual respective packets, the packet descriptors comprising a memory address of packet data.

20. The processor readable storage medium of claim 19 ,

wherein the multiple receive queues comprise network controller queues.

21. The processor readable storage medium of claim 19 ,

wherein the multiple receive queues comprise host memory queues.

22. The method of claim 1 , wherein each individual packet descriptor further comprises length data.

23. The method of claim 7 , wherein each individual packet descriptor further comprises length data.

24. The network controller of claim 11 , wherein each individual packet descriptor further comprises length data.

25. The network controller of claim 11 , wherein the bus comprises a Peripheral Component Interconnect type bus.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 5, 2022
From: INTEL CORPORATION
To: MEDIATEK INC.
Reel/Frame 059828/0105 →
Continuity (3)
Continuation 11141917 · Jun 1, 2005
Division 10044989 · Jan 15, 2002
Related Publication 20110208871A1 · Aug 25, 2011