Continuous time delta sigma converter having a VCO based quantizer

1. A continuous-time delta sigma converter, comprising:

a loop filter including a plurality of serially coupled integrators including a first integrator responsive to an input of the Delta Sigma converter and a last integrator responsive to a first feedback loop and providing an integrated output signal; and

a voltage controlled oscillator (VCO) based quantizer responsive to the loop filter for integrating the integrated output signal and providing a digital output signal;

the first feedback loop including a first time delay circuit responsive to the output of the quantizer and at least one switched capacitor digital to analog converter (DAC) responsive to the first time delay circuit, the first feedback loop configured to differentiate the digital output signal twice and provide the last integrator of the loop filter with a double differentiated analog signal to reduce excess loop delay.

2. The delta sigma converter of claim 1 in which at least one switched capacitor DAC includes a first switched capacitor DAC responsive to the first time delay circuit, and a second switched capacitor DAC responsive to the output of the quantizer.

3. The delta sigma converter of claim 2 in which each switched capacitor DAC includes:

a plurality of switches each responsive to a reference voltage;

a plurality of capacitances each responsive to at least one of the plurality of switches; and

at least one output switch responsive to the plurality of capacitances and a clock signal for providing an output signal from the switched capacitor DAC.

4. The delta sigma converter of claim 3 in which each of the capacitances are responsive to first and second switches which are respectively responsive to first and second reference voltages.

5. The delta sigma converter of claim 4 in which the first switch is clocked by an output bit of the quantizer and the second switch is clocked by a complementary signal of the output bit.

6. The delta sigma converter of claim 3 in which each switch includes an inverter responsive to an output of the quantizer, the reference voltage is a supply voltage for the inverter, and each of the capacitances are responsive to a corresponding inverter.

7. The delta sigma converter of claim 1 in which the first time delay circuit delays the output signal from the quantizer by approximately half of a clock cycle.

8. The delta sigma converter of claim 1 in which the loop filter includes second and third integrators coupled in series between the first and last integrators.

9. The delta sigma converter of claim 8 in which the loop filter includes three feedforward capacitances each coupled between an input of one of the three integrators and the output of the loop filter.

10. The delta sigma converter of claim 1 in which the loop filter includes one or more feedforward capacitances coupled to the output of the loop filter.

11. The delta sigma converter of claim 1 in which the loop filter includes a resonator stage.

12. The delta sigma converter of claim 1 further including a second feedback loop coupled between the output of the quantizer and an input of the loop filter, the second feedback loop including a current steering DAC responsive to the quantizer.

13. The delta sigma converter of claim 12 in which the second feedback loop further includes a second time delay circuit coupled between the quantizer and the current steering DAC for delaying the output signal from the quantizer by approximately half of a clock cycle.

14. A continuous-time delta sigma converter, comprising:

a loop filter including four serially coupled integrators including a first integrator responsive to an input of the Delta Sigma converter and a fourth integrator responsive to a first feedback loop and providing an integrated output signal; and

a voltage controlled oscillator (VCO) based quantizer responsive to the loop filter for integrating the integrated output signal and providing a digital output signal;

the first feedback loop configured to differentiate the digital output signal twice and provide the fourth integrator with a double differentiated analog signal to reduce excess loop delay, the first feedback loop including:

a first time delay circuit responsive to the output of the quantizer,

a first switched capacitor DAC responsive to the first time delay circuit, and

a second switched capacitor DAC responsive to the output of the quantizer.

15. The delta sigma converter of claim 14 in which the first time delay circuit delays the output signal from the quantizer by approximately half of a clock cycle.

16. The delta sigma converter of claim 14 in which the first and second switched capacitor DACs differentiate in a continuous time domain, and in which the first time delay circuit delays the digital output signal and the output of the first switched capacitor DAC is subtracted from the output of the second switched capacitor DAC such that differentiation also occurs in a discrete time domain.

17. The delta sigma converter of claim 16 in which the loop filter includes one or more feedforward capacitances coupled to the output of the loop filter.

18. The delta sigma converter of claim 17 in which there are three feedforward capacitances each coupled between an input of one of the three integrators and the output of the loop filter.

19. The delta sigma converter of claim 14 further including a second feedback loop coupled between the output of the quantizer and an input of the loop filter, the second feedback loop including a current steering DAC responsive to the quantizer.

20. The delta sigma converter of claim 19 in which the second feedback loop further includes a second time delay circuit coupled between the quantizer and the current steering DAC for delaying the output signal from the quantizer by approximately half of a clock cycle.

21. A switched capacitor digital to analog converter (DAC) responsive to a quantizer in a feedback loop of a continuous-time delta sigma converter, the switched capacitor DAC comprising:

a plurality of switches each responsive to a reference voltage;

a plurality of capacitances each responsive to a first switch and a second switch which are respectively responsive to first and second reference voltages;

at least one output switch responsive to the plurality of capacitances and a clock signal for providing an output signal from the switched capacitor DAC; and

the first switch clocked by an output bit of the quantizer and the second switch clocked by a complementary signal of the output bit.

22. The delta sigma converter of claim 21 in which there is only one output switch.

23. The delta sigma converter of claim 21 in which each switch includes an inverter responsive to an output of the quantizer, the reference voltage is a supply voltage for the inverter, and each of the capacitances are responsive to a corresponding inverter.