Variable resistance memory devices and methods of manufacturing the same

1. A method of manufacturing a variable resistance memory device, the method comprising:

forming an ohmic layer on a substrate;

forming a sacrificial pattern on the ohmic layer;

forming a preliminary first electrode pattern,

the preliminary first electrode pattern including a first portion and a second portion,

the second portion of the preliminary first electrode pattern contacting a sidewall of the sacrificial pattern; and

forming a preliminary ohmic pattern by removing a portion of the ohmic layer exposed by the sacrificial pattern and the preliminary first electrode pattern;

exposing a sidewall of the first electrode pattern by removing the sacrificial pattern,

the first portion of the preliminary first electrode pattern contacting the preliminary ohmic pattern;

forming a preliminary first spacer pattern on a sidewall of the preliminary first electrode pattern;

forming an ohmic pattern by etching the preliminary ohmic pattern; and

forming a variable resistance pattern and a second electrode pattern on the ohmic pattern.

2. The method of claim 1 , further comprising:

forming an insulation layer on the substrate, the insulation layer having a hole that exposes a top of the substrate;

forming a first semiconductor pattern doped with a first impurity having a first conductive type to partially fill the hole;

forming a second semiconductor pattern on the first semiconductor pattern to completely fill the hole,

the second semiconductor pattern doped with a second impurity of a second conductive type being different from the first conductive type;

forming a metal layer on the second semiconductor pattern and the insulation layer; and

thermally treating the second semiconductor pattern and the metal layer to transform a top of the second semiconductor pattern contacting the metal layer into a conductive pattern including a metal semiconductor compound.

3. The method of claim 2 , wherein the forming of the preliminary first electrode pattern comprises:

conformally forming a first electrode layer on the ohmic layer and the sacrificial pattern;

forming a preliminary second spacer pattern on a sidewall of the sacrificial pattern having the first electrode layer; and

forming the preliminary first electrode pattern by etching the first electrode layer with the preliminary second spacer pattern used as an etch mask,

wherein the preliminary second spacer pattern is formed to cover a top of the conductive pattern formed at a bottom of the preliminary first electrode pattern.

4. The method of claim 1 , wherein

the preliminary first spacer pattern is formed to cover a top of a conductive pattern formed at a bottom of the preliminary ohmic pattern.

5. The method of claim 1 , wherein

the sacrificial pattern is formed of a material having an etch selectivity with respect to the preliminary first spacer pattern and the first electrode pattern when an etchant is used.

6. The method of claim 1 , wherein the forming the ohmic layer includes:

sequentially stacking a metal layer and a metal compound layer.

7. A method of manufacturing a variable resistance memory device comprising:

forming an ohmic layer connected to at least one word line;

forming at least one sacrificial pattern on the ohmic layer;

forming a first electrode layer on the at least one sacrificial pattern and the ohmic layer;

forming at least one preliminary first spacer pattern on the first electrode layer and the ohmic layer;

forming at least one ohmic pattern by,

removing a first portion of the ohmic layer using at least the at least one preliminary first spacer pattern as a mask, and

removing a second portion of the ohmic layer under the at least one sacrificial pattern; and

forming at least one variable resistance pattern and at least one second electrode pattern on the at least one ohmic pattern.

8. The method of manufacturing a variable resistance memory device of claim 7 , wherein the forming at least one preliminary first spacer pattern forms the at least one preliminary first spacer pattern so

the first electrode layer is between the at least one sacrificial pattern and the at least one preliminary first spacer pattern, and

the first electrode layer is between the ohmic layer and the at least one preliminary first spacer pattern.

9. The method of manufacturing a variable resistance memory device of claim 7 , wherein the forming an ohmic layer connected to at least one word line includes:

forming at least one select device on the at least one word line; and

forming the ohmic layer on the at least one select device.

10. The method of manufacturing a variable resistance memory device of claim 7 , wherein

the forming at least one ohmic pattern further includes,

forming at least one preliminary first electrode pattern by removing an exposed portion of the first electrode layer; and

the removing the second portion of the ohmic layer under the at least one sacrificial pattern includes,

removing the at least one sacrificial pattern,

forming at least one preliminary second spacer pattern on a sidewall of the preliminary first electrode pattern, and

removing the second portion of the ohmic layer using at least the at least one preliminary second spacer pattern as a mask.

11. The method of manufacturing a variable resistance memory device of claim 7 , wherein

the forming at least one ohmic pattern further includes removing a third portion of the ohmic layer.